tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 434

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADACLK
(0xFFFF_F81C)
16.2 Conversion Clock
Example: If fsys = fc = 40 MHz
fc
Variable S/H time
fc
40MHz
Conversion
clock
40MHz
clock ≤ 40MHz) .
The conversion time is calculated by the 46 conversion clock at the minimum (conversion
bit Symbol
Read/Write
After reset
Function
÷1
S/H time
Conversion clk*8(0.2us)
Conversion clk*16(0.4us)
Conversion clk*24(0.6us)
Conversion clk*32(0.8us)
Conversion clk*64(1.6us)
Conversion clk*128 (3.2us)
Conversion clk*512 (12.8us)
Select the A/D sample hold time
÷2
1000: 8 conversion clock
1010: 24 conversion clock
0011: 64 conversion clock
1100: 128 conversion clock
Other than the above: reserved
prescaler
1
1/2
1/4
TSH3
R/W
7
1
A/D Conversion Clock Setting Register
÷4
tSH2
R/W
6
TMP19A61 (rev1.0)16-433
0
÷8
1011: 32 conversion clock
1101: 512 conversion clock
1001: 16 conversion clock
tSH1
R/W
5
÷16
0
Tconv.
(Conversion time)
1.15μs
2.3μs
4.6μs
ADDCLK2:0
Tconv.
(Conversion time)
1.15μs
1.35μs
1.55μs
1.75μs
2.55μs
4.15μs
13.75μs
tSH0
R/W
4
0
“0” is read.
3
R
0
Select the A/D prescaler output
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
111: Reserved
ADCLK2
R/W
2
0
ADCLK
TMP19A61
ADCLK1
R/W
1
0
ADCLK0
R/W
0
0