tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 445

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.3.1
17.3 Control Registers
Watchdog Timer Mode Register (WDMOD)
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
This is a 2-bit register for specifying the watchdog timer interrupt time for runaway
detection. When a reset is effected, this register is initialized to WDMOD <WDTP1, 0>
= "00." 17.3.1 shows the detection time of the watchdog timer.
When reset, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the
disable code (B1H) must be written to the WDCR register. This dual setting is intended
to minimize the probability that the watchdog timer may inadvertently be disabled if a
runaway occurs.
To change the status of the watchdog timer from "disable" to "enable," set the
<WDTE> bit to "1."
This is a register for specifying the connection of non-maskable interrupt (INTWDT) or
an internal reset after a runaway is detected. As a reset initializes this setting to
WDMOD <RESCR>="0" and non-maskable interrupt is specified. Refer to the part of
NMIFLG register in Chapter 6 “Interrupt”.
Specifying the detection time of the watchdog timer <WDTP1: 0>
Enabling/disabling the watchdog timer <WDTE>
Watchdog timer out reset connection <RESCR>
TMP19A61
(rev1.0)
-17-444
TMP19A61