tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 407

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.6.3
SCL
SDA
<PIN>
INTSBI
interrupt
request
Transferring a Data Word
(Note) The user can only use a DMA transfer:
At the end of a data word transfer, the INTSBI interrupt is generated to test <MST> to
determine whether the SBI is in the master or slave mode.
Fig. 15.6.2.1 Generation of the Start Condition and a Slave Address
Start
condition
Slave mode
In the slave mode, the SBI receives the start condition and a slave address.
Master mode (<MST> = "1")
Test <TRX> to determine whether the SBI is configured as a transmitter or a receiver.
Transmitter mode (<TRX> = "1")
Test <LRB>. If <LRB> is "1," that means the receiver requires no further data. The
master then generates the stop condition as described later to stop transmission.
If <LRB> is "0," that means the receiver requires further data. If the next data to be
transmitted has eight bits, the data is written into SBI0DBR. If the data has different
length, <BC2:0> and <ACK> are programmed and the transmit data is written into
SBI0DBR. Writing the data makes <PIN> to"1," causing the SCL pin to generate a
serial clock for transfer of a next data word, and the SDA pin to transfer the data word.
After the transfer is completed, the INTSBI interrupt request is generated, <PIN> is set
to "0," and the SCL pin is pulled to the "L" level... To transmit more data words, test <LRB> again
and repeat the above procedure.
After receiving the start condition from the master device, the SBI receives a slave
address and a direction bit from the master device during the first eight clocks on the
SCL line. If the received address matches its slave address specified at I2CAR or is
equal to the general-call address, the SBI pulls the SDA line to the "L" level during the
ninth clock and outputs an acknowledgment signal.
The INTS0 interrupt request is generated on the falling of the ninth clock, and <PIN> is
cleared to "0." In the slave mode, the SBI holds the SCL line at the "L" level while
<PIN> is "0."
• when there is only one master and only one slave and
• continuous transmission or reception is possible.
A6
1
A5
TMP19A61
2
A4
3
Slave address + Direction bit
(
rev1.0
A3
4
)
-15-406
A2
5
A1
6
A0
7
TMP19A61
R/
W
8
Master to slave
Slave to master
ACK
9
Aknowledgeme
nt from slave