tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 279

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

11.2.2 Up-counter (UC0) and Up-counter Capture Registers (TBxxUCL, TBxxUCH)
11.2.3 Timer Registers (TBxxRG0H/L, TBxxRG1H/L)
This is the 16-bit binary counter that counts up in response to the input clock specified by
TBxxMOD<TB0CLK1:0>.
UC0 input clock can be selected from either three types - φT1, φT4 and φT16 - of prescaler
output clock or the external clock of the TBxxIN0 pin. For UC0, start, stop and clear are
specified by TB0RUN<TB0RUN> and if UC0 matches the TBxxRG1H / L timer register, it is
cleared to “0” provided the setting is “clear enable.” Clear enable/disable is specified by
TBxxMOD<TB0CLE>.
If the setting is “clear disable,” the counter operates as a free-running counter.
The current count value of the UC0 can be captured by reading the TBxxUCL andTBxxUCH
registers.
If UC0 overflow occurs, the INTTBxx overflow interrupt is generated.
is activated by TB0CRUN<TB0CUDCE>. This counter serves as the up-down counter, and
is initialized to 0x7FFF. If a counter overflow occurs, the initial value 0x0000 is reloaded. If
a counter underflow occurs, the initial value 0xFFFF count is reloaded.
two-phase pulse count mode is not active, the counter counts up only.
These are 16-bit registers for specifying counter values and two registers are built into each
channel. If a value set on this timer register matches that on a UC0 up-counter, the match
detection signal of the comparator becomes active.
To write data to the TBxxRG0H/L and TBxxRG1H/L timer registers, either a 2-byte data
transfer instruction or a 1-byte data transfer instruction written twice in the order of
low-order 8 bits followed by high-order 8 bits can be used.
TBxxRG0 of this timer register is paired with register buffer 0 - a double-buffered
configuration. TBxxRG0 uses TBxxRUN<TB0RDE> to control the enabling/disabling of
double buffering. If <TB0RDE> = “0,” double buffering is disabled and if <TB0RDE> = “1,” it
is enabled. If double buffering is enabled, data is transferred from register buffer 0 to the
TBxxRG0 timer register when there is a match between UC0 and TBxxRG1.
The values of TBxxRG0 and TBxxRG1 become undefined after a reset; therefore it is
necessary to write data to them beforehand in case of using a 16-bit timer. A reset initializes
TB0RUN <TB0RDE> to “0” and sets double buffering to “disable.” To use double buffering,
write data to the timer register, set <TB0RDE> to “1” and then write the following data to the
register buffers.
TBxxRG0
0xFFFF_FxxA/0xFFFF_FxxB. If <TB0RDE> = “0,” the same value is written to TBxxRG0
and each register buffer; if <TB0RDE> = “1,” the value is only written to each register buffer.
To write an initial value to the timer register, therefore, the register buffers must be set to
“disable.”
TMRB0C has the two-phase pulse input count function. The two-phase pulse count mode
(Note) Make sure that reading is performed in the order of
low-order bits followed by high-order bits.
and
the
TMP19A61 (rev 1.0)11-278
register
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TMP19A61
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