tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 441

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

16.3.5
16.3.6
16.3.7
High-priority Conversion Mode
A/D Monitor Function
Storing and Reading A/D Conversion Results
By interrupting ongoing normal A/D conversion, top-priority A/D conversion can be
performed. Top-priority A/D conversion can be software activated by setting
ADAMOD2<HPADCE> to "1" or it can be activated using the HW resource by setting
ADAMOD4<7:6> to an appropriate setting. If top-priority A/D conversion has been
activated during normal A/D conversion, ongoing normal A/D conversion is interrupted,
and single conversion is performed for a channel designated by ADAMOD2<3:0>. The
result of single conversion is stored in ADAREGSP, and the top-priority A/D conversion
interrupt is generated. After top-priority A/D conversion is completed, normal A/D
conversion is resumed; the status of normal A/D conversion immediately before being
interrupted is maintained. Top-priority A/D conversion activated while top-priority A/D
conversion is under way is ignored.
For example, if channel repeat conversion is activated for channels ANA0 through ANA8
and if <HPADCE> is set to "1" during ANA3 conversion, ANA3 conversion is suspended,
and conversion is performed for a channel designated by <HPADC3:0>. After the result
of conversion is stored in ADAREGSP, channel repeat conversion is resumed, starting
from ANA3.
If ADAMOD3<ADOBSV> is set to "1," the A/D monitor function is enabled. If the value of
the conversion result storage register specified by REGS<3:0> becomes larger or
smaller ("larger" or "smaller" to be designated by ADOBIC) than the value of a
comparison register, the A/D monitor function interrupt is generated. This comparison
operation is performed each time a result is stored in a corresponding conversion result
storage register, and the interrupt is generated if the conditions are met. Because storage
registers assigned to perform the A/D monitor function are usually not read by software,
overrun flag <OVRn> is always set and the conversion result storage flag <ADRnRF> is
also set. To use the A/D monitor function, therefore, a flag of a corresponding conversion
result storage register must not be used.
A/D conversion results are stored in upper and lower A/D conversion result registers for
normal A/D conversion (ADAREG08H/L through ADARG7FH/L).
In fixed channel repeat conversion mode, A/D conversion results are sequentially stored
in ADAREG08H/L through ADAREG7FH/L. If <ITM1:0> is so set as to generate the
interrupt each time one A/D conversion is completed, conversion results are stored only
in ADAREG08H/L. If <ITM1:0> is so set as to generate the interrupt each time four A/D
conversions are completed, conversion results are sequentially stored in ADAREG08H/L
through ADAREG3BH/L.
Table 16.3.7 shows analog input channels and related A/D conversion result registers.
TMP19A61 (rev1.0)16-440
TMP19A61