tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 254

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(6) Combinations of transfer modes
(7) Address changes
Address changes are broadly classified into three types: increases, decreases and fixed. The type of
address change can be specified for each source and destination address by using SAC and DAC in
the CCRn register. If a single transfer is selected as a source or destination device, SAC or DAC in the
CCRn register must be set to "fixed".
If address increase or decrease is selected, the bit position for counting can be specified using SACM
for the source address or DACM for the destination address in the DTCRn register. To specify the bit
position for counting a source address, any of the bits 0, 4, 8, 12 and 16 can be specified as the bit
position for address counting. If 0 is selected, an address increases or decreases as per normal. By
selecting bits 4, 8, 12 or 16, it is possible to increase or decrease an address irregularly.
Examples of address changes are shown below.
The DMAC can transfer data by combining each transfer mode as follows:
Transfer
request
Example 1: Monotonic increase for a source device and irregular increase for a
destination device
External
External
Internal
1st 0xA000_1000 0xB000_0000
2nd 0xA000_1004 0xB000_0010
3rd 0xA000_1008 0xB000_0020
4th 0xA000_100C 0xB000_0030
SAC: Address increase
DAC: Address increase
TrSiz: Transfer unit 32 bits
Source address: 0xA000_1000
Destination address: 0xB000_0000
SACM: 000 → counting to begin from bit 0 of the address counter
DACM: 001 → counting to begin from bit 4 of the address counter
Source
Edge/level
(INTDREQn)
Falling edge
-
(DREQn)
(DREQn)
“L” level
“L” level
TMP19A61 (rev1.0)10-253
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Destination
-
Address mode
Dual
Transfer type
Continuous
Continuous
Single
Single
TMP19A61