tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 256

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

− Level mode
DREQn
A[31:1]
DACKn
A transfer request made by the interrupt controller (INTC)
A transfer request made by an external device
The DACKn signal can clear a transfer request made by the interrupt controller. This DACKn
signal is asserted only if a bus cycle for a single transfer or the number of bytes (value set in the
BCRn register) transferred at continuous transfer becomes "0." Therefore, at the single transfer,
the amount of data specified by TrSiz is transferred only once because INTDREQn is cleared
upon completion of one data transfer from one transfer request. On the other hand, at the
continuous transfer, it can be transferred successively in response to a transfer request because
becomes "0."
External pins (
port Q. These pins can be selected by setting the function control register PQFC to an
appropriate setting.
INTDREQn is not cleared until the number of bytes transferred (value set in the BCRn register)
Note that there is a possibility that the DMA transfer might be executed once after the interrupt is
cleared depending on the timing if the DMAC acknowledges an interrupt set in INTDREQn and
this interrupt is cleared by the INTC before the DMA transfer begins.
In the edge mode, the DREQn signal must be negated and then asserted for each transfer
request to create an effective edge. In the level mode, however, successive transfer requests
can be recognized by maintaining an effective level. At continuous transfer, only the "L" level
mode can be used. At single transfer, only the falling edge mode can be used.
In the level mode, the DMAC detects the "L" level of the DREQn signal upon the rising of the
internal system clock. If it detects the "L" level of the DREQn signal when a channel is in a
standby mode, it goes into transfer mode and starts to transfer data. To use the DREQn signal
at an active level, the PosE bit (bit 13) of the CCRn register must be set to "0." The DACKn
signal is active at the "L" level, as in the case of the DREQn signal.
If an external circuit asserts the DREQn signal, the DREQn signal must be maintained at the
"L" level until the DACKn signal is asserted. If the DREQn signal is negated before the
If the DREQn signal is not at the "L" level, the DMAC judges that there is no transfer request,
and starts a transfer operation for other channels or releases bus the control authority and goes
into a standby mode.
The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register.
DACKn signal is asserted, a transfer request may not be recognized.
DREQ
Fig. 10.13 Transfer Request Timing (Level Mode)
3
and
TMP19A61 (rev1.0)10-255
DREQ ) are internally wired to allow them to function as pin of the
2
Data transfer
TMP19A61