tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 46

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.8
6.8.1
The maskable hardware interrupts (hereinafter referred to as "hardware interrupts") are 63 factor
interrupt requests for which the interrupt controller (INTC) can individually assign one of seven interrupt
(priority) levels.
In order for a hardware interrupt request to be accepted, it is necessary regarding the CP0 register that
its Status <IE> is set to "1" and Status <ERL/EXL> is cleared to "0" while Status <IM [4:2]> is set to "1."
If more than one interrupts are generated at the same time, the hardware interrupts are accepted in
accordance with the priority order of the interrupt levels. If more than one interrupts of a same interrupt
level are generated at the same time, these interrupts are accepted in the order of the interrupt number
as listed in Table 6.2.
When an interrupt request is accepted, the Status <EXL> bit of the CP0 register is set to "1," further
interrupts are disabled, and ILEV<CMASK> of INTC is automatically updated to the interrupt level set
for the interrupt request. Note that Status <IE> of the CP0 register remains set to "1" in interrupt
response operations.
In processing hardware interrupts, each interrupt level is associated with a register bank called a
"shadow register set" which is enabled when CP0 register SSCR<SSD>=”0”. When an interrupt request
is accepted, the register bank is switched to the register bank of which number is the same as with the
corresponding interrupt level. Through this mechanism, it is unnecessary for the user program to save
the general purpose register (GPR) contents elsewhere upon interrupt response thus ensuring fast
interrupt response.
For accepting multiple interrupts, Status <EXL> of the CP0 register is cleared to "0" to permit further
interrupts. In this, because ILEV <CMASK> of INTC has been updated to the interrupt level set for the
interrupt request already accepted, only further interrupts of which level is higher than the present
interrupt level can be accepted. Refer to Section 6.9.3 "Example of Multiple Interrupt Setting" for more
details of multiple interrupts.
Also, by appropriately setting the ILEV <CMASK> register of INTC, you can mask interrupt requests of
which interrupt level is lower than a programmed mask level.
Any interrupt request can be used as a trigger to start a DMA transfer sequence.
While detailed operation of hardware interrupts is provided below, please also refer to the section
"Exception Handling, Maskable Interrupts (Interrupts)" of the separate volume "TX19A Core
Architecture" for more details.
Maskable Hardware Interrupts
TX19A
Core
Features
Notification
Response
Fig. 6.3 Interrupt Notification Diagram
INTC
TMP19A61(rev1.0)-6-45
CG
Interrupts to clear
stand-by
Other interrupts
TMP19A61