tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 235

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.2.2 DMAC Internal Blocks
10.2.3 Snoop Function
is given higher priority than GREQ.
The TX19A processor core has a snoop function. If the snoop function is activated, the TX19A
processor core opens the core's data bus to the DMAC and suspends its own operation until the DMAC
withdraws a request for bus control authority. If the snoop function is enabled, the DMAC can access the
internal RAM and ROM and therefore designate the RAM or ROM as a source or destination.
If the snoop function is not used, the DMAC cannot access the internal RAM or ROM. However, the
G-Bus is opened to the DMAC. If the TX19A processor core attempts to access memory by way of the
G-Bus, bus operations cannot be executed and, as a result, the pipeline stalls unless the DMAC accept
a bus control release request.
Fig. 10.2 shows the internal blocks of the DMAC.
(Note) If the snoop function is not used, the TX19A processor core does not open the data
bus to the DMAC. If the data bus is closed and the internal RAM or ROM is
designated as a DMAC source or destination, an acknowledgment signal will not be
returned in response to a DMAC transfer bus cycle and, as a result, the bus will lock.
Channel 7
Channel 6
Channel 5
Channel 4
Channel 3
Fig.10.2 DMAC Internal Blocks
TMP19A61 (rev1.0)10-234
Channel 2
Channel 1
Channel 0
31
Source address register (SARx)
Destination address register (DARx)
Byte count register (BSRx)
Channel control register (CCRx)
Channel status register (CSRx)
DMA transfer control register (DTCRx)
DMA control register (DCR)
Request select register (RSR)
Data holding register (DHR)
（ x＝ 0~7）
TMP19A61
0