tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 381

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.3
14.3.1
Operation in Each Mode
Mode 0 (I/O Interface Mode)
Mode 0 consists of two modes, i.e., the "HSCLK output" mode to output synchronous clock
and the "HSCLK input" mode to accept synchronous clock from an external source. The
following operational descriptions are for the case use of FIFO is disabled. For details of FIFO
operation, refer to the previous sections describing receive/transmit FIFO functions.
HSCLK output mode
Transmitting data
In the HSCLK output mode, if HSC0MOD2<WBUF> is set to "0" and the transmit
double buffers are disabled, 8 bits of data are output from the HXD0 pin and the
synchronous clock is output from the HSCLK0 pin each time the CPU writes data to
the transmit buffer. When all data is output, the HINTTX0 interrupt is generated.
If HSC0MOD2 <WBUF> is set to "1" and the transmit double buffers are enabled, data
is moved from Transmit Buffer 2 to Transmit Buffer 1 when the CPU writes data to
Transmit Buffer 2 while data transmission is halted or when data transmission from
Transmit Buffer 1 (shift register) is completed. When data is moved from Transmit
Buffer 2 to Transmit Buffer 1, the transmit buffer empty flag HSC0MOD2 <TBEMP> is
set to "1," and the HINTTX0 interrupt is generated. If Transmit Buffer 2 has no data to
be moved to Transmit Buffer 1, the HINTTX0 interrupt is not generated and the
HSCLK0 output stops.
TMP19A61(rev. 1.0) 14-380
TMP19A61