tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 243

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8 : 7
5 : 4
3 : 2
1 : 0
Bit
10
9
6
(Note 1) The CCRn register setting must be completed before the DMAC is put into a
standby mode.
(Note 2) When accessing the internal I/O or transferring data by DMA in response to the
DREQ pin request, make sure that you set the transfer unit <TrSiz> size to be the same
as the device port size <DPS>.
(Note 3) In executing memory-to-memory data transfer, a value set in DPS becomes
invalid.
Mnemonic
Reserved
RelEn
TrSiz
SAC
DAC
DPS
SIO
Bus
request enable
Transfer type selection
Source Address Count
(Reserved)
Destination
count
Transfer unit
Device port size
Fig. 10.4 Channel Control Register (CCRn) (2/2)
Field name
control
TMP19A61 (rev1.0)10-242
address
release
Release Request Enable (initial value: 0)
Acknowledgment of the bus control release request made by the
TX19A processor core is specified. This function is valid only if
GREQ is generated. This function cannot be used if SREQ is
generated since the TX19A processor core cannot make a bus
control release request.
1: The bus control release request is acknowledged if the DMAC
0: The bus control release request is not acknowledged.
Source Type: continuous (initial value: 0)
Specifies the transfer type.
1: Single transfer
0: Continuous transfer
Source Address Count (initial value: 00)
Specifies the manner of change in a source address.
1x: Address fixed
01: Address decrease
00: Address increase
Always set this bit to “0”.
Destination Address Count (initial value: 00)
Specifies the manner of change in a destination address.
1x: Address fixed
01: Address decrease
00: Address increase
Transfer Size (initial value: 00)
Specifies the amount of data to be transferred in response to one
transfer request.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4bytes)
Device Port Size (initial value: 00)
Specifies the bus width of an I/O device designated as a source or
destination device.
11: 8 bits (1 byte)
10: 16 bits (2bytes)
0x: 32 bits (4 bytes)
has control of the bus. If the TX19A processor core issues a bus
control release request, the DMAC relinquishes control of the bus
to the TX19A processor core at the break of bus operation.
Description
TMP19A61