tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 355

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Master controller setting
Slave controller setting
Main routine
PCCR
PCFC
IMC3
SC0MOD0 ← 1 0 1 0 1 1 1 0
SC0BUF
Interrupt routine (INTTX0)
INTCLR
SC0MOD0 ← 0
SC0BUF
interrupt
processing is
completed.
Main routine
PCCR
PCFC
PCODE
IMC3
SC0MOD0 ← 0 0 1 1 1 1 1 0
Interrupt routine (INTRX0)
INTCLR
Reg.
if Reg. = Select code
Then
SC0MOD0 ←
← SC0BUF
←
←
←
←
← 0 0 0 0 0 0 0 1
← * * * * * * * *
←
←
←
←
←
0 0 0 1 1 1 1 0 0
0 0 0 1 1 1 0 0 0
− − − − − −
− − − − − −
−
−
− − − − − −
− − − − − −
− − − − − − −
−
−
− − −
− − − − − − −
1 1
1 1
1 1
1 1
TMP19A61 (rev1.0)-13-354
−
−
−
−
0
− − − −
0 1 0 1
0 1 0 0
0 1 1 0
0 1 0 1
0 1
1 1
0 1
1 1
1
Designates PC0 as TXD (open drain output) and P61 as RXD.
Sets the 9-bit UART mode and f
<WU> to "1."
Sets the 9-bit UART mode and f
Sets the select code of Slave 1.
Clears the interrupt request. (0x0000_003C).
Sets TB8 to "0."
Sets the data to be sent.
Enables INTTX0 and INTRX0...
Clears the interrupt request.
Clears <WU> to "0."
Designates PC0/PC1 as the TXD0/RXD0 pins, respectively.
Enables the INTRX0 interrupt and sets to level 5 by the
<23:16> bits of the 32 bit register.
Enables the INTTX0 interrupt and sets to level 4 by the
<31:24> bits of the 32 bit register.
SYS
SYS
TMP19A61
/2 transfer clock.
/2 transfer clock and sets