tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 208

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(3) Time that it takes before ALE is asserted
(assert time) can be specified by using the bus control register BUSCR<ALESEL1:0> in
the CS/ wait controller. In the case of a separate bus mode, ALE is not output, but the
time from when an address is established to the assertion of the RD or
different depending on the BUSCR<ALESEL1:0>.
During a reset, <ALESEL1:0> = "01" is set and the RD or
point of one system (internal) clock after an address is established. If <ALESEL1:0> is
cleared to "00," the RD or
assert setting cannot be established for each block in an external area and the same
setting is commonly used in an external address space.
When the external bus of the TMP19A61 is used as a multiplexed bus, the ALE width
A［23:0］
D[15:0]
RD
Fig. 8. 8 ALE Assert Timing in Separate Bus Mode
<ALESEL>="0"
TMP19A61(rev1.0)-8-207
address
tsys
data
WR
signal is asserted after an address is established. This
<ALESEL>="1"
address
data
WR
TMP19A61
signal is asserted at a
WR
signal is