tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 375

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_E806)
HSC0MOD2
<SWRST1:0>: Overwriting "01" in place of "10" generates a software reset. When this software reset
<WBUF>: This parameter enables or disables the transmit/receive buffers to transmit (in both
<DRCHG>: Specifies the direction of data transfer in the I/O interface mode. In the UART mode, it is
<TXRUN>: This is a status flag to show that data transmission is in progress.
<RBFLL>: This is a flag to show that the receive double buffers are full. When a receive operation is
<TBEMP>: This flag shows that the transmit double buffers are empty. When data in the transmit
<SBLEN>: This specifies the length of stop bit transmission in the UART mode. On the receive side,
(Note 1) While data transmission is in progress, any software reset operation must be
Bit symbol
Read/Write
After reset
Function
executed twice in succession. The registers must be byte accessed
in setting them.
is executed, the mode register parameters HSC0MOD0<RXE>, HSCMOD1<TXE> ，
HSC0MOD2<TBEMP>,<RBFLL>,<TXRUN>,
HSC0CR<OERR>, <PERR>, <FERR>, and their internal circuits are initialized.
HSCLK output/input modes) and receive (in HSCLK output mode) data in the I/O interface
mode and to transmit data in the UART. In all other modes, double buffering is enabled
regardless of the <WBUF> setting.
fixed to LSB first.
When this bit is set to "1," it indicates that data transmission operation is in progress. If it is
"0," the bit 7 <TBEMP> is set to "1" to indicate that the transmission has been fully
completed and the same <TBEMP> is set to "0" to indicate that the transmit buffer
contains some data waiting for the next transmission.
completed and received data is moved from the receive shift register to the receive
double buffers, this bit changes to "1" while reading this bit changes it to "0."
If double buffering is disabled, this flag is insignificant.
double buffers is moved to the transmit shift register and the double buffers are empty,
this bit is set to "1." Writing data again to the double buffers sets this bit to "0."
If double buffering is disabled, this flag is insignificant.
the decision is made using only a single bit regardless of the <SBLEN> setting.
Transmit
buffer
empty flag
0: full
1: Empty
TBEMP
7
1
Fig. 14.12 Serial Mode Control Register
Receive
buffer full
FLAG
0: Empty
1: full
TMP19A61(rev. 1.0) 14-374
RBFLL
6
0
In
transmission
flag
0: Stop
1: Start
TXRUN
5
0
R/W
STOP bit
0: 1-bit
1: 2-bit
SBLEN
4
0
1: MSB first
Setting
transfer
direction
0: LSB first
DRCHG
control
3
0
1: Enable
W-buffer
0: Disable
WBUF
2
0
register
TMP19A61
Soft reset
Overwrite "01" on "10"
to reset
SWRST1
Ｗ
1
0
parameters
SWRST0
Ｗ
0
0