tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 339

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

<CNFG>: If enabled, the SCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows:
<FDPX1:0>= 01 (Half duplex RX) ---- 4-byte RX FIFO
<FDPX1:0>=10 (Half duplex TX) ---- 4-byte TX FIFO
<FDPX1:0>=11 (Full duplex) ---- 2-Byte RX FIFO + 2-Byte TX FIFO
<RXTXCNT>:0 The function to automatically disable RXE/TXE bits is disabled.
<FDPX1:0>= 01 (Half duplex RX) ------When the RX FIFO is filled up with the specified number of valid bytes;
<FDPX1:0>= 10 (Half duplex TX) ------When the TX FIFO is empty, TXE is automatically set to "0" to inhibit
<FDPX1:0>= 11 (Full duplex) -----------When either of the above two conditions is satisfied, TXE/RXE are
<RFIE>: When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter.
<TFIE>: When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter.
<RFST>: When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected.
(0xFFFF_F70C)
(0xFFFF_F700)
SC0FCNF
SC0BUF
(Note 1) Regarding TX FIFO, the maximum number of bytes being configured is always
(Note)
: 1 If enabled, the SCOMOD1 <FDPX1:0> is used to set as follows:
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
0:
1:
available.
The available number of bytes is the bytes already written to the TX FIFO.
SC0BUF works as a transmit buffer for WR operation and as a receive
buffer for RD operation.
Be sure to write "000."
Fig. 13.4.6 SIOO Transmit/ Receive Buffer Register
The maximum number of bytes of the FIFO configured 4 bytes when <FDPX1:0>
= 01 (Half duplex RX) and 2 bytes for <FDPX1:0> = 11 (Full duplex)
Same as the fill level for receive interrupt generation specified by SC0RFC
<RIL1:0>.
TB7/RB7
7
0
7
0
Fig. 13.4.7 FIFO Configuration Register
TMP19A61 (rev1.0)-13-338
TB6/RB6
automatically set to "0" to inhibit further transmission and reception.
RXE is automatically set to "0" to inhibit further reception.
further transmission.
6
6
0
0
TB5/RB5
5
5
0
0
TB7 to TB0: Transmit buffer + FIFO
RB7 to RB0: Receive buffer + FIFO
1: Same as
Bytes
used in RX
FIFO
0: Maximum
TB4/RB4
Fill level
of RX
FIFO
RFST
4
4
0
0
R/W
R/W
1: Enable
TX
interrupt
for TX
FIFO
0: Disable
TB3/RB3
TFIE
3
3
0
0
1: Enable
RX
interrupt
for RX
FIFO
0: Disable
TB2/RB2
RFIE
2
2
0
0
TMP19A61
1: Auto
Automatic
disable of
RXE/TXE
0: None
RXTXCNT
TB1/RB1
disable
1
1
0
0
FIFO
Enable
0: Disable
1: Enable
TB0/RB0
CNFG
0
0
0
0