tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 427

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADAMOD4
(0xFFFF_F818)
ADAMOD3
(0xFFFF _F817)
(Note 2) Do not make a top-priority A/D conversion setting and a normal A/D conversion
(Note 3) The external trigger cannot be specified as HW source for activating normal A/D
(Note 4) Software reset initializes all the bits of the mode registers. Therefore, resetting
(Note 1) If A/D conversion is executed with the match triggers <ADHTG> and <HADHTG>
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
of a 16-bit timer set to "1" by using a source for triggering H/W, A/D conversion
can be activated at specified intervals by performing three steps shown below
when the timer is idle:
setting simultaneously.
conversion when it is specified as HW source for activating top-priority A/D
conversion.
these values is required.
<REGS.2, 1, 0>
Write “0”.
HW source for
activating
top-priority
A/D
conversion
0: External
1: Match with
TB9RG0
HADHS
TRG
Select a source for triggering HW: <ADHS>, <HADHS>
Enable H/W activation of A/D conversion: <ADHTG>, <HADHTG>
Start the timer.
R/W
7
7
0
0
0000
0001
0010
0011
0100
0101
0110
“0” is read.
HW for
activating
top-priority
A/D
conversion
0: Disable
1: Enable
HADHTG
TMP19A61 (rev1.0)16-426
6
R
0
6
0
A/D Mode Control Register 3
A/D Mode Control Register 4
R/W
Make AD
monitor
function
interrupt
setting
0: Smaller
1: Larger
HW source for
activating
normal A/D
conversion
0: External
1: Match with
TB1RG0
ADOBIC
TRG
than
compariso
n Register
than
compariso
n Register
ADHS
０
5
5
0
AD conversion
Register to be
result storage
ADAREG2A
ADAREG3B
ADAREG4C
ADAREG5D
ADAREG6E
ADAREG08
ADAREG19
compared
BIT for selecting the AD conversion result storage Register that
is to be compared with the comparison Register if the AD
monitor function is enabled
HW for
activating
normal A/D
conversion
0: Disable
1: Enable
REGS3
ADHTG
０
4
4
0
“0” is read.
REGS2
０
3
3
R/W
R
0
REGS1
０
2
2
TMP19A61
Overwriting 10 with 01 allows
ADC to be software reset.
ADRST1
REGＳ0
０
W
−
1
1
AD monitoring
function
0: Disable
1: Enable
ADOBSV
ADRST0
０
Ｗ
−
0
0