tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 85

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.9.4.5
INTCLR
(0xFFFF_E060)
(Note 1)
(Note 3)
(Note 2)
When it is desired to clear any interrupt request being suspended, you can do so by setting the IVR [7:0]
for the corresponding interrupt factor into the INTCLR register. When an interrupt request is cleared, the
IVR value is also cleared and the interrupt factor cannot be determined anymore. Do not clear an interrupt
request before reading the IVR value.
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Set the IVR <IVR7:0> value that corresponds to the interrupt request that you would like to clear
Interrupt Request Clear Registers (INTCLR)
(1)
(2)
(3)
(4)
Bit Symbol
Read/Write
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
Clear the interrupt request regardless of the active state setting of INTC IMCx
<EIMxx>, i.e., either "H" level, "L" level, rising edge, or falling edge, in order to
maintain interrupt factors.
Bit manipulation instructions cannot be used to access this register.
External transfer requests due to DMAC interrupt factors are not cleared. Once an
external transfer request is accepted, it will not be canceled until the DMA transfer is
executed. Therefore, any unnecessary external transfer request should be cleared
by executing DMA transfer or disabling interrupts using IMCx <ILxxx> or by
canceling the corresponding DMAC activation factors using IMCx<DMxx> before
accepting the external transfer requests.
Be sure to clear the corresponding interrupt number with INTCLR after setting
IMCx register.
Please ensure that the type of active state is selected before enabling an interrupt
request.
When making interrupt requests DMAC activation factors, please ensure that you
put the DMAC into standby mode after setting the INTC.
An active condition must be changed after putting the interrupt output of the
corresponding device into the state of negate especially when it is changed to the
level detection.
Change the setting from IL="other than 0" to IL=”0”.
Change the detection condition (EIM).
Clear corresponding interrupt by INTCLR.
Set IL to "other than 0".
EICLR7
Set the IVR <IVR7:0> value that corresponds to the interrupt request that you would like to clear.
15
23
31
7
0
EICLR6
TMP19A61(rev1.0)-6-84
22
30
14
6
0
EICLR5
13
21
29
5
0
EICLR4
12
Always reads “0.”
20
Always reads “0.”
28
Always reads “0.”
4
0
R/W
R
R
R
0
0
0
EICLR3
11
19
27
3
0
EICLR2
10
18
26
2
0
TMP19A61
EICLR1
17
25
1
0
9
EICLR0
16
24
0
8
0