tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 406

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.6 Data Transfer Procedure in the I
15.6.1
15.6.2
Device Initialization
Generating the Start Condition and a Slave Address
Settings in main routine
Example of INTSBI interrupt routine
First, program SBI0CR1<ACK, SCK2:0> by writing "0" to bits 7 to 5 and bit 3 in SBI0CR1.
Next, program I2CAR by specifying a slave address at <SA6:0> and an address
recognition mode at <ALS>. (<ALS> must be set to"0" when using the addressing format.)
Next, program SBI0CR2 to initially configure the SBI in the slave receiver mode by writing
"0" to <MST, TRX, BB> , "1" to <PIN> , "10" to <SBIM1:0> and "0" to bits 1 and 0.
INTCLR ← 0X50
Processing
End of interrupt
SBI0CR1 ← 0 0 0 X 0 X X X
I2CAR
SBI0CR2 ← 0 0 0 1 1 0 0 0
(Note) X: Don’t care
Reg.
Reg.
if Reg.
Then
SBI0CR1 ← X X X 1 0 X X X
SBI0DR1 ← X X X X X X X X
SBI0CR2 ← 1 1 1 1 1 0 0 0
Master mode
In the master mode, the following steps are required to generate the start condition
and a slave address.
First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBI0CR1 <ACK> to
select the acknowledgment mode. Write to SBI0DBR a slave address and a direction
bit to be transmitted.
When <BB> = "0," writing "1111" to SBI0CR2 <MST, TRX, BB, PIN> generates the
start condition on the bus. Following the start condition, the SBI generates nine clocks
from the SCL pin. The SBI outputs the slave address and the direction bit specified at
SBI0DBR with the first eight clocks, and releases the SDA line in the ninth clock to
receive an acknowledgment signal from the slave device.
The INTSBI interrupt request is generated on the falling of the ninth clock, and <PIN>
is cleared to "0." In the master mode, the SBI holds the SCL line at the "L" level while
<PIN> is "0." <TRX> changes its value according to the transmitted direction bit at
generation of the INTSBI interrupt request, provided that an acknowledgment signal
has been returned from the slave device.
≠ 0x00
← X X X X X X X X
← SBISR
← Reg. e 0x20
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
TMP19A61
2
C Bus Mode
(
rev1.0
Specifies ACK and SCL clock.
Specifies a slave address and an address recognition
mode.
Configures the SBI as a slave receiver.
Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
Clears the interrupt request.
)
-15-405
TMP19A61