tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 405

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.5.14 Software Reset
15.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR)
15.5.16 I
15.5.17 IDLE Setting Register (SBI0BR0)
2
C Bus Address Register (I2CAR)
If the serial bus interface circuit locks up due to external noise, it can be initialized by using
a software reset.
Writing "10" followed by "01" to SBI0CR2 <SWRST1:0> generates a reset signal that
initializes the serial bus interface circuit. After a reset, all control registers and status flags
are initialized to their reset values. When the serial bus interface is initialized, <SWRST> is
automatically cleared to "0."
(Note) A software reset causes the SBI operating mode to switch from the I
Reading or writing SBI0DBR initiates reading received data or writing transmitted data.
When the SBI is acting as a master, setting a slave address and a direction bit to this
register generates the start condition.
When the SBI is configured as a slave device, the I2CAR<SA6:0> bit is used to specify a
slave address. If I2C0AR <ALS> is set to "0," the SBI recognizes a slave address
transmitted by the master device and receives data in the addressing format. If <ALS> is
set to "1," the SBI does not recognize a slave address and receives data in the free data
format.
The SBI0BR0<I2SBI> register determines if the SBI operates or not when it enters the
IDLE mode. This register must be programmed before executing an instruction to switch to
the standby mode.
to the port mode.
TMP19A61
(
rev1.0
)
-15-404
TMP19A61
2
C mode