tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 397

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SBI0CR2
(0xFFFF_F603)
(Note 1)
(Note 2)
bit Symbol
Read/Write
After reset
Function
Reading this register causes it to function as the SBISR register.
Ensure that the bus is free before switching the operating mode to the port mode.
Ensure that the port is at the "H" level before switching the operating mode from the
port mode to the I
Select
master/slave
0: Slave
1: Master
MST
7
0
Select
transmit/
receive
0: Receive
Serial bus interface control register 2
1: Transmit
Table 15.4.4 Base Clock Resolution
Fig. 15.4.3 I
2
TRX
C bus or clock-synchronous 8-bit SIO mode.
TMP19A61
6
Clock gear value
0
<GEAR2:0>
100 (fc/2)
110 (fc/4)
111 (fc/8)
000 (fc)
W
Start/stop
condition
generation
0: Stop
1: Start
generated
condition
generated
condition
BB
2
5
0
C Bus Mode Register
(
rev1.0
@fsys = 54 MHz
fsys/2
fsys/2
fsys/2
fsys/2
Clear INTSBI
interrupt
request
0: −
1: Clear
Base clock
resolution
interrupt
request
PIN
4
1
)
2
3
4
5
-15-396
(0.07 μ s)
(0.14 μ s)
(0.28 μ s)
(0.58 μ s)
Select serial bus interface operating mode (Note 2)
00 Port mode (Serial bus interface output disabled)
01 Clock-synchronous 8-bit SIO mode
10 I
11 (Reserved)
Select serial bus interface
operating mode
(Note 2)
00: Port mode
01: SIO mode
10: I
11: (Reserved)
SBIM1
2
3
C bus mode
0
2
C bus mode
W
SBIM0
2
0
TMP19A61
Software reset generation
Write "10" followed by "01"
to generate a reset.
SWRST1
1
0
W
SWRST0
0
0