tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 315

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.2
SCLK0 input
(Shared with
PF2)
SCLK0
output
(Shared with
PF2)
RXD0
(Shared with
PF1)
FIFO control
f
SYS
φT0
Block Diagram (Channel 0)
/2
SC0MOD0
<RXE>
φT1
φT4
φT16
φT64
RB8
I/O interface mode
Serial clock generation circuit
RXDCLK
(÷ 16 only with UART)
<BR0CK1, 0>
Receive buffer 1 (shift register)
φ T1
Receive counter
BR0CR
2
Receive buffer 2(SC0BUF)
Receive control
Internal data bus
4
<BR0S3 : 0>
φT4
Prescaler
BR0CR
8
Baud rate
generator
16 32 64
<BR0ADDE>
φT16 φT64
BR0CR
Fig. 13.2.1 SIO0 Block Diagram
SC0MOD0
<WU>
<OERR><PERR><FERR>
<BR0K3 : 0>
TMP19A61 (rev1.0)-13-314
128
BR0ADD
<PE>
Parity control
SC0CR
Error flag
÷ 2
SC0CR
interrupt control
<EVEN>
(From TMRB4)
channel
Serial
TB4OUT
SC0MOD0
<SC1, 0>
SC0CR
<IOC>
Internal data bus
I/O interface mode
UART
mode
SC0MOD0
<SM1, 0>
Transmit buffer 1 (shift register)
TXDCLK
TB8
(÷ 16 only with UART)
Transmit counter
Transmit control
Internal data bus
SIOCLK
Transmit buffer
TMP19A61
SC0MOD0
<CTSE>
FIFO control
Interrupt request
INTRX0
Interrupt
request INTTX0
(Shared with
PF2)
TXD0
(Shared with
PF0)
CTS
0