tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 396

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SBI0CR1
(0xFFFF_F600)
(Note 1)
(Note 2)
(Note 3)
bit Symbol
Read/Write
After reset
Function
Clear
clock-synchronous 8-bit SIO mode.
After a reset, the <SCK0/SWRMON> bit is read as "1." However, if the SIO mode is
selected at the SBICR2 register, the initial value of the <SCK0> bit is "0."
For details on the SCL line clock frequency, refer to "15.5.3 Serial Clock."
Select the number of bits per
transfer (Note 1)
<BC2:0>
BC2
7
0
Serial bus interface control register 1
Fig. 15.4.2 I
BC1
R/W
to
TMP19A61
6
0
"000"
BC0
2
5
0
C Bus Mode Register
before
(
rev1.0
Acknowled
gment
clock
0: Not
1: Generate
generate
ACK
R/W
4
0
)
-15-395
switching
On writing <SCK2:0>: Select internal SCL output clock frequency
On reading <SWRMON> Software reset condition monitor
Select the number of bits per transfer
000
001
010
011
100
101
110
111
<BC2:0>
0
1
000
001
010
011
100
101
110
111
n=10
n=11
n=5
n=6
n=7
n=8
n=9
Software reset operation is in progress.
Software reset operation is not in progress.
3
R
1
clock cycles
Number of
the
265 kHz
201 kHz
136 kHz
reserved
13 kHz
83 kHz
46 kHz
25 kHz
Select internal SCL output clock
frequency
monitor
8
1
2
3
4
5
6
7
<ACK> = 0
SCK2
operation
2
0
R/W
length
System clock: fsys
Clock gear
Frequency =
Data
TMP19A61
(Note
8
1
2
3
4
5
6
7
SCK1
1
0
2)
clock cycles
mode
Number of
2
fsys/2
n
and
+ 70
9
2
3
4
5
6
7
8
SWRMON
<ACK> = 1
SCK0/
R/W
0
1
: fc/1
reset
to
(=54 MHz)
[ Hz ]
length
Data
the
8
1
2
3
4
5
6
7