tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 368

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.11 Transmit FIFO Buffer
14.1.12 Transmit FIFO Operation
I/O interface mode with HSCLK output (normal mode):
Transmit Buffer 1
Transmit Buffer 2
TX FIFO
In addition to the double buffer function already described, data may be stored using the
transmit FIFO buffer. By setting <HCNFG> of the HSC0FCNF register and <FDPX1:0>
of the HSC0MOD1 register, the 4-byte transmit buffer can be enabled. In the UART mode
or I/O interface mode, up to 4 bytes of data may be stored.
generation
duplex, writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1."
When the last transmit data is moved to the transmit buffer, the transmit FIFO interrupt is
generated. When transmission of the last data is completed, the clock is stopped and the
transmission sequence is terminated.
The following example describes the case a 4-byte data stream is transmitted:
HSC0TFC <7:6> = 01: Clears transmit FIFO and sets the condition of interrupt
HSC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0.
HSC0FCNF <1:0> = 01011: Inhibits continued transmission after reaching the fill level.
In this condition, data transmission can be initiated by setting the transfer mode to half
TBEMP
INTTX0
TXE
Fig. 14-8 Transmit FIFO Operation
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
TMP19A61(rev 1.0)14-367
Data 3
Data 5
Data 4
Data 2
Data 6
Data 4
Data 6
Data 5
Data 3
Data 5
Data 6
Data 4
Data 6
Data 5
TMP19A61