tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 521

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note:
5) Automatic chip erase (per 512KB)
6) Automatic block erase (128 kB at a time)
bus write cycle of the automatic page programming command.
The automatic chip erase operation starts when the sixth bus write cycle of the command
cycle is completed.
The automatic block erase operation starts when the sixth bus write cycle of the command
cycle is completed.
This status of the automatic block erase operation can be checked by monitoring FLCS [0]
<RDY/BSY> (See Table 22.6). While no automatic verify operation is performed internally to
the device, be sure to read the data to confirm that data has been correctly erased. Any new
command sequence is not accepted while it is in an automatic block erase operation. If it is
desired to stop operation, use the hardware reset function. In this case, it is necessary to
perform the automatic block erase operation again because the data erasing operation has
not been normally terminated.
Also, any protected blocks cannot be erased. If an automatic block erase operation has
automatic page programming to process input data across pages.
Data cannot be written to a protected block. When automatic programming is finished, it
automatically returns to the read mode. This condition can be checked by monitoring FLCS
[0] <RDY/BSY> (See Table 22.16). If automatic programming has failed, the flash memory
is locked in the mode and will not return to the read mode. For returning to the read mode, it
is necessary to use the reset command or hardware reset to reset the flash memory or the
device. In this case, while writing to the address has failed, it is recommended not to use the
device or not to use the block that includes the failed address.
This condition can be checked by monitoring FLCS [0] <RDY/BSY> (See Table 22.16).
While no automatic verify operation is performed internally to the device, be sure to read the
data to confirm that data has been correctly erased. Any new command sequence is not
accepted while it is in an automatic chip erase operation. If it is desired to stop operation,
use the hardware reset function. If the operation is forced to stop, it is necessary to perform
the automatic chip erase operation again because the data erasing operation has not been
normally terminated.
Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic
chip erase operation will not be performed and it returns to the read mode after completing
the sixth bus read cycle of the command sequence. When an automatic chip erase
operation is normally terminated, it automatically returns to the read mode. If an automatic
chip erase operation has failed, the flash memory is locked in the mode and will not return to
the read mode.
For returning to the read mode, it is necessary to use the reset command or hardware reset
to reset the flash memory or the device. In this case, the failed block cannot be detected. It
is recommended not to use the device anymore or to identify the failed block by using the
block erase function for not to use the identified block anymore.
Software reset becomes ineffective in bus write cycles on and after the fourth
TMP19A61 (rev1.0) 22-520
TMP19A61