tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 363

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.1.6
14.1.7
Receive FIFO Buffer
Receive FIFO Operation
Receive buffer 2
Receive buffer 1
Receive interrupt
I/O interface mode with HSCLK output
The following example describes the case a 4-byte data stream is received in the half duplex
mode:
HSC0RFC<7:6>=01: Clears receive FIFO and sets the condition of interrupt generation.
HSC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.
HSC0FCNF <1:0>=10111: Automatically inhibits continued reception after reaching the fill
level.
The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill
level.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing "1" to the RXE bit. After receiving 4 bytes, the RXE bit is automatically
cleared and the receive operation is stopped (HSCLK is stopped)
RX FIFO
In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting <CNFG> of the HSC0FCNF register and <FDPX1:0> of the
HSC0MOD1 register, the 4-byte receive buffer can be enabled. Also, in the UART mode or
I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO
buffer is to be used, be sure to enable the double buffer function.
RBFLL
RXE
Fig. 14-3 Receive FIFO Operation
1 byte
TMP19A61(rev. 1.0) 14-362
1 byte
2 byte
1 byte
3 byte
2 byte
1 byte
2 byte
3 byte
4 byte
3 byte
2 byte
1 byte
TMP19A61
4 byte
4 byte
3 byte
2 byte
1 byte