tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 206

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2 waits automatically inserted + 2N (N=1)
3 waits automatically inserted + 2N (N=1)
2 waits automatically inserted + 2N (N=2)
2 waits automatically inserted
0 wait
waits automatically inserted + external waits are inserted in the separate bus mode.
Fig. 8.6 shows the write operation timing when 0 wait, waits automatically inserted, and
fsys
A[23:0]
D[15:0]
A[23:0]
D[15:0]
A[23:0]
D[15:0]
A[23:0]
D[15:0]
A[23:0]
D[15:0]
/WAIT
/WAIT
/WAIT
/WAIT
/WAIT
/WR
/WR
/WR
/WR
/WR
Fig. 8.6 Write Operation Timing Diagram
--- External wait sampling point
External wait sampling points take place before a cycle of waits automatically
inserted is finished and before a 2N_wait cycle is finished as shown above.
The same applies to combinations of other numbers of waits.
TMP19A61(rev1.0)-8-205
2 waits automatically
automatically
automatically
tsys
3 waits automatically
inserted
inserted
2 waits
2 waits
inserted
inserted
2N_WAIT
2N_WAIT
2N_WAIT
TMP19A61