tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 257

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DREQn
A[31:1]
DACKn
− Edge mode
In the edge mode, the DMAC detects the falling edge of the DREQn signal. If it detects the
falling edge of the DREQn signal upon the rising of the internal system clock (the case in which
the "L" level is detected upon the rising of the system clock although it was not detected upon the
rising of the previous system clock) when a channel is in a standby mode, it judges that there is
a transfer request, goes into transfer mode, and starts a transfer operation. To detect the falling
edge of the DREQn signal, the PosE bit (bit 13) of the CCRn register must be set to "0," and the
Lev bit (bit 12) must also be set to "0." The DACKn signal is active at the "L" level.
If the falling edge of the DREQn signal is detected after the DACKn signal is asserted, the next
data is transferred without a pause.
If there is no falling edge of the DREQn signal after the DACKn signal is asserted, the DMAC
judges that there is no transfer request, and starts a transfer operation for other channels or
goes into a standby mode after releasing bus control authority.
The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register.
Fig. 10.14 Transfer Request Timing (Edge Mode)
TMP19A61 (rev1.0)10-256
Data transfer
Data transfer
TMP19A61