tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 352

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Main routine settings
An example of interrupt routine process
Reg.
if Reg. ≠ 0 then ERROR processing
Reg.
Interrupt processing is completed.
(Note) X: don’t care
PCCR
PCFC
SC0MOD ←
SC0CR
BR0CR
IMC3
SC0MOD ←
INTCLR
← SC0CR AND 0x1C
← SC0BUF
←
←
← X 0 1 X X X 0 0
← 0 0 0 1 0 1 0 1
←
0 0 0 1 1 1 0 0 0
− − − − − −
− − − − − −
−
−
− −
7 6 5 4 3 2 1 0
0 0 X 1 0 0 1
1 1
Interrupt process start
TMP19A61 (rev1.0)-13-351
1 X
SC0BUF data read
−
Interrupt process
complete
SC0CR=0x1C?
INTCLR=0x
− − − −
0 1 0 0
− : no change
0
1
−
−
Yes
Reads received data.
Designates PC1 as the RXD0 pin.
Selects the 8-bit UART mode.
Sets odd parity.
Sets the data rate to 9600 bps.
Enables the INTRX0 interrupt and sets to level 4 by the
<23:16> bits of the 32 bit register.
Enables reception of data.
Clears the interrupt request. (0x0000_0038)
Performs error check.
No
Error
processing
TMP19A61