tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 492

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

21.3 JTAG Controller and Registers
21.3.1 Instruction Register
In the JTAG basic mechanism, the TAP controller state machine monitors the signals input through
the JTMS pin. As the JTAG mechanism starts operation, the TAP controller determines a test
function to be executed by loading data into the JTAG instruction register (IR) and performing a serial
data scan via the data register (DR), as shown in Table 21.1. When data is scanned, the state of the
JTMS pin represents new specific data words and the end of data flow. The data register is selected
according to data loaded into the instruction register.
The following JTAG controller and registers are built into the processor:
Most significant to least
MSB
•
•
•
•
•
The JTAG instruction register consists of four cells, including shift registers. It is used to select
either a test to be executed or a test data register to be accessed or to select both. Either the
boundary scan register or the bypass register is selected according to combinations shown in
Table 21.1.
Instruction code
Fig. 21.3 shows the format of the instruction register.
significant bit
Instruction register
Boundary scan register
Bypass register
Device identification register
Test Access Port (TAP) controller
0010 ~1110
3
0000
0001
1111
Table 21.1 Bit Configurations of the JTAG Instruction Register
TMP19A61 (rev1.0)21 -491
Fig. 21.3 Instruction register
SAMPLE/PRELOAD
Instruction
Reserved
BYPASS
EXTEST
2
Data register to be selected
Boundary scan register
Boundary scan register
1
Bypass register
Reserved
TMP19A61
LSB
0