tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 53
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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TMP19A61F10XBG
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6.8.5
When a hardware interrupt is generated, the TX19A core will go through the following steps to jump to
the corresponding exception vector address as given in Table 6.1 according to the Status <BEV> and
Cause <IV> bits of the CP0 register.
Hardware Interrupt Operation
(1) Sets Status <EXL> of CP0 register to "1."
(2) Sets the PC value at the interrupt generation to EPC of the CP0 register.
(3) If the shadow register set is enabled (CP0 register SSCR <SSD> = 0), SSCR
(4) The values of ILEV <CMASK/PMASKx> of INTC will be updated and the mask level is
(5) Sets IVR [7:0] to the corresponding value listed in Table 6.2.
<CSS/PSS> of the CP0 register will be updated and it switches to the register bank of
the same interrupt level number.
set to the interrupt level of the interrupt request accepted.
TMP19A61(rev1.0)-6-52
TMP19A61
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