MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet

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MMC2107CFCPV33

Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet

Specifications of MMC2107CFCPV33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
MMC2107/D
REV 2
MMC2107
Technical Data
HCMOS
Microcontroller Unit

MMC2107CFCPV33 Summary of contents

Page 1

MMC2107/D REV 2 MMC2107 Technical Data HCMOS Microcontroller Unit ...

Page 2

... Freescale Semiconductor, Inc. blank For More Information On This Product, Go to: www.freescale.com ...

Page 3

... Freescale Semiconductor, Inc. MMC2107 Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...

Page 4

... Freescale Semiconductor, Inc. Technical Data Technical Data 4 For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MMC2107 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 43 Section 2. System Memory Map . . . . . . . . . . . . . . . . . . . 51 Section 3. Chip Configuration Module (CCM Section 4. Signal Description 107 Section 5. Reset Controller Module 129 Section 6. M•CORE M210 Central Processor Section 7. Interrupt Controller Module . . . . . . . . . . . . . 153 Section 8. Static Random-Access Memory Section 9 ...

Page 6

... Freescale Semiconductor, Inc. List of Sections Section 16. Serial Communications Interface Section 17. Serial Peripheral Interface Section 18. Queued Analog-to-Digital Section 19. External Bus Interface Module (EBI 503 Section 20. Chip Select Module . . . . . . . . . . . . . . . . . . . 521 Section 21. JTAG Test Access Port and OnCE . . . . . . 533 Section 22. Electrical Specifications 585 Section 23. Mechanical Specifications . . . . . . . . . . . . . 609 Section 24 ...

Page 7

... Freescale Semiconductor, Inc. Technical Data — MMC2107 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Block Diagram ...

Page 8

... Freescale Semiconductor, Inc. Table of Contents 3.7 3.7.1 3.7.2 3.7.3 3.7.3.1 3.7.3.2 3.7.3.3 3.7.3.4 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.9 3.10 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.4 Technical Data 8 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Programming Model ...

Page 9

... Freescale Semiconductor, Inc. 4.5.3 4.5.3.1 4.5.3.2 4.5.3.3 4.5.3.4 4.5.3.5 4.5.3.6 4.5.3.7 4.5.3.8 4.5.3.9 4.5.3.10 4.5.3.11 4.5.4 4.5.4.1 4.5.4.2 4.5.4.3 4.5.5 4.5.5.1 4.5.5.2 4.5.5.3 4.5.5.4 4.5.6 4.5.6.1 4.5.6.2 4.5.7 4.5.8 4.5.8.1 4.5.8.2 4.5.8.3 4.5.8.4 4.5.9 4.5.9.1 4.5.9.2 4.5.9.3 4.5.9.4 4.5.9.5 4.5.9.6 MMC2107 – Rev. 2.0 ...

Page 10

... Freescale Semiconductor, Inc. Table of Contents 4.5.10 4.5.11 4.5.11.1 4.5.11.2 4.5.11.3 4.5.11.4 4.5.11.5 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.8 Technical Data 10 Test Signal (TEST 128 Power and Ground Signals ...

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... Freescale Semiconductor, Inc. 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.7.2.1 7.7.2.2 7.7.2.3 7.7.2.4 7.7.2.5 7.7.2.6 7.7.2.7 7.7.2.8 7.7.2.9 7.8 7.8.1 7.8.2 7.8.3 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 6. M• ...

Page 12

... Freescale Semiconductor, Inc. Table of Contents 7.8.4 7.8.4.1 7.8.4.2 7.8.4.3 7.8.5 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.5 9.6 9.7 9.7.1 9.7.1.1 9.7.1.2 9.7.1.3 9.7.2 9.7.2.1 9.7.2.2 Technical Data 12 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 M•CORE Processor Configuration . . . . . . . . . . . . . . . . . 171 Interrupt Controller Configuration ...

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... Freescale Semiconductor, Inc. 9.8 9.8.1 9.8.2 9.8.3 9.8.4 9.8.4.1 9.8.4.2 9.8.4.3 9.8.4.4 9.8.4.5 9.8.5 9.8.5.1 9.8.5.2 9.8.5.3 9.8.6 9.8.7 9.9 9.10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.4.1 10.4.4.2 10.5 10.6 10.6.1 10.6.2 10.6.3 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Functional Description ...

Page 14

... Freescale Semiconductor, Inc. Table of Contents 10.6.4 10.6.5 10.7 10.7.1 10.7.2 10.7.2.1 10.7.2.2 10.7.2.3 10.7.2.4 10.8 10.8.1 10.8.2 10.8.3 10.8.3.1 10.8.3.2 10.8.4 10.8.4.1 10.8.4.2 10.8.5 10.8.6 10.8.6.1 10.8.6.2 10.8.6.3 10.8.6.4 10.9 10.10 Interrupts 246 11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.2.1 11.4.2.2 ...

Page 15

... Freescale Semiconductor, Inc. 11.4.2.3 11.4.2.4 11.4.2.5 11.4.2.6 11.5 11.5.1 11.5.2 11.6 12.1 12.2 12.3 12.3.1 12.3.2 12.4 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.2.3 12.5.2.4 12.5.2.5 12.5.2.6 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Port Pin Data/Set Data Registers ...

Page 16

... Freescale Semiconductor, Inc. Table of Contents 13.4 13.5 13.6 13.6.1 13.6.2 13.6.2.1 13.6.2.2 13.6.2.3 13.6.2.4 Section 14. Programmable Interrupt Timer Modules 14.1 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.6 14.6.1 14.6.2 14.6.2.1 14.6.2.2 14.6.2.3 14.7 14.7.1 14.7.2 14.7.3 14.8 Technical Data 16 Block Diagram ...

Page 17

... Freescale Semiconductor, Inc. 15.1 15.2 15.3 15.4 15.5 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.6 15.6.1 15.6.2 15.7 15.7.1 15.7.2 15.7.3 15.7.4 15.7.5 15.7.6 15.7.7 15.7.8 15.7.9 15.7.10 Timer Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . 309 15.7.11 Timer System Control Register 310 15.7.12 Timer Flag Register 312 15 ...

Page 18

... Freescale Semiconductor, Inc. Table of Contents 15.8 15.8.1 15.8.2 15.8.3 15.8.4 15.8.4.1 15.8.4.2 15.8.5 15.9 15.10 Interrupts 326 15.10.1 Timer Channel Interrupts (CxF 326 15.10.2 Pulse Accumulator Overflow (PAOVF 327 15.10.3 Pulse Accumulator Input (PAIF 327 15.10.4 Timer Overflow (TOF 327 Section 16. Serial Communications Interface Modules 16 ...

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... Freescale Semiconductor, Inc. 16.7.8 16.7.9 16.8 16.9 16.10 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 16.11 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 16.11.1 Frame Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 16.11.2 Transmitting a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 16.11.3 Break Frames 355 16.11.4 Idle Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 16.12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 16.12.1 Frame Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 16.12.2 Receiving a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 16 ...

Page 20

... Freescale Semiconductor, Inc. Table of Contents Section 17. Serial Peripheral Interface Module (SPI) 17.1 17.2 17.3 17.4 17.5 17.6 17.6.1 17.6.2 17.6.3 17.6.4 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.7.8 17.8 17.8.1 17.8.2 17.8.3 17.8.3.1 17.8.3.2 17.8.4 17.8.5 17.8.6 17.8.7 17.8.7.1 17 ...

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... Freescale Semiconductor, Inc. 17.9 17.10 Interrupts 397 17.10.1 SPI Interrupt Flag (SPIF 397 17.10.2 Mode Fault (MODF) Flag . . . . . . . . . . . . . . . . . . . . . . . . . . 397 18.1 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.6 18.6.1 18.6.1.1 18.6.1.2 18.6.2 18.6.2.1 18.6.2.2 18.6.3 18.6.4 18.6.5 18.6.6 18.6.7 18.7 18.8 18.8.1 18 ...

Page 22

... Freescale Semiconductor, Inc. Table of Contents 18.8.5 18.8.5.1 18.8.5.2 18.8.5.3 18.8.6 18.8.6.1 18.8.6.2 18.8.7 18.8.8 18.8.8.1 18.8.8.2 18.8.8.3 18.9 18.9.1 18.9.2 18.9.2.1 18.9.2.2 18.9.2.3 18.9.3 18.9.3.1 18.9.3.2 18.9.3.3 18.9.3.4 18.9.3.5 18.9.3.6 18.9.3.7 18.9.3.8 18.9.3.9 18.10 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 18.10.1 Queue Priority Timing Examples 450 18 ...

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... Freescale Semiconductor, Inc. 18.10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 18.10.6.1 18.10.6.2 18.10.6.3 18.10.6.4 18.10.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 472 18.10.7.1 18.10.7.2 18.10.7.3 18.10.7.4 18.10.8 QADC Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . 476 18.10.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .480 18.10.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . .481 18.10.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 18.11 Pin Connection Considerations . . . . . . . . . . . . . . . . . . . . . . .486 18 ...

Page 24

... Freescale Semiconductor, Inc. Table of Contents 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.10 Chip Selects (CS[3:0 507 19.3.11 Output Enable (OE 507 19.3.12 Transfer Size (TSIZ[1:0 507 19.3.13 Processor Status (PSTAT[3:0 507 19.4 19.5 19.6 19.7 19.7.1 19.7.1.1 19.7.1.2 19.7.1.3 19.7.2 19.7.2.1 19.7.2.2 19.7.2.3 19 ...

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... Freescale Semiconductor, Inc. 20.4 20.5 20.6 20.6.1 20.6.2 20.7 20.8 21.1 21.2 21.3 21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 21.3.6 21.4 21.5 21.5.1 21.5.2 21.5.3 21.5.4 21.5.5 21.5.6 21.5.7 21.6 21.7 21.8 21.9 21.10 Non-Scan Chain Operation 547 21.11 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 21.12 Low-Level TAP (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . .553 MMC2107 – ...

Page 26

... Freescale Semiconductor, Inc. Table of Contents 21.13 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555 21.13.1 Debug Serial Input (TDI 555 21.13.2 Debug Serial Clock (TCLK 555 21.13.3 Debug Serial Output (TDO 555 21.13.4 Debug Mode Select (TMS 556 21.13.5 Test Reset (TRST 556 21.13.6 Debug Event (DE 556 21 ...

Page 27

... Freescale Semiconductor, Inc. 21.14.10 Enabling OnCE Trace Mode . . . . . . . . . . . . . . . . . . . . . . .575 21.14.11 Enabling OnCE Memory Breakpoints 576 21.14.12 Pipeline Information and Write-Back Bus Register . . . . . . 576 21.14.12.1 Program Counter Register . . . . . . . . . . . . . . . . . . . . . . .577 21.14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . 579 21 ...

Page 28

... Freescale Semiconductor, Inc. Table of Contents 23.1 23.2 23.3 23.4 23.5 23.6 23.7 24.1 24.2 24.3 Technical Data 28 Section 23. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Bond Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 Package Information for the 144-Pin LQFP . . . . . . . . . . . . . . 611 Package Information for the 100-Pin LQFP . . . . . . . . . . . . . . 611 144-Pin LQFP Mechanical Drawing ...

Page 29

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Figure 1-1 2-1 2-2 3-1 3-2 3-3 3-4 3-5 4-1 4-2 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Title Block Diagram ...

Page 30

... Freescale Semiconductor, Inc. List of Figures Figure 7-6 7-7 7-8 7-9 7-10 7-11 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 11-1 11-2 11-3 11-4 11-5 11-6 11-7 Technical Data 30 Title Interrupt Pending Register (IPR 162 Normal Interrupt Enable Register (NIER) ...

Page 31

... Freescale Semiconductor, Inc. Figure 11-8 11-9 12-1 12-2 12-3 12-4 12-5 12-6 12-7 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Title Digital Input Timing ...

Page 32

... Freescale Semiconductor, Inc. List of Figures Figure 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 Technical Data ...

Page 33

... Freescale Semiconductor, Inc. Figure 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 MMC2107 – Rev. 2.0 ...

Page 34

... Freescale Semiconductor, Inc. List of Figures Figure 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 18-24 18-25 18-26 18-27 18-28 18-29 18-30 18-31 18-32 18-33 18-34 18-35 18-36 18-37 18-38 18-39 18-40 18-41 18-42 18-43 18-44 18-45 18-46 18-47 18-48 ...

Page 35

... Freescale Semiconductor, Inc. Figure 18-49 18-50 18-51 18-52 18-53 18-54 19-1 19-2 19-3 19-4 19-5 19-6 20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Title Gated Mode, Continuous Scan Timing ...

Page 36

... Freescale Semiconductor, Inc. List of Figures Figure 21-14 21-15 21-16 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 22-12 22-13 Technical Data 36 Title Control State Register (CTL .578 OnCE PC FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Recommended Connector Interface to JTAG/OnCE Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 V versus Programming Time . . . . . . . . . . . . . . . . . . . . . 595 ...

Page 37

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Table 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 4-2 5-1 5-2 5-3 6-1 7-1 7-2 7-3 7-4 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Title Register Address Location Map ...

Page 38

... Freescale Semiconductor, Inc. List of Tables Table 7-5 7-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 12-1 12-2 13-1 Technical Data 38 Title Vector Table Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Interrupt Source Assignment ...

Page 39

... Freescale Semiconductor, Inc. Table 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 SCI Interrupt Request Sources .369 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 MMC2107 – Rev. 2.0 ...

Page 40

... Freescale Semiconductor, Inc. List of Tables Table 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 Non-Multiplexed Channel Assignments 18-11 Multiplexed Channel Assignments 18-12 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 18-13 Trigger Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 18-14 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 18-15 QADC Clock Programmability . . . . . . . . . . . . . . . . . . . . . . .479 ...

Page 41

... Freescale Semiconductor, Inc. Table 21-5 21-6 21-7 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 FLASH EEPROM Module Life Characteristics . . . . . . . . . . . 594 22-11 External Interface Timing Characteristics 596 22-12 Reset and Configuration Override Timing . . . . . . . . . . . . . . 601 22-13 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 602 22-14 OnCE, JTAG, and Boundary Scan Timing ...

Page 42

... Freescale Semiconductor, Inc. List of Tables Technical Data 42 List of Tables For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 43

... Freescale Semiconductor, Inc. Technical Data — MMC2107 1.1 Contents 1.2 1.3 1.4 1.2 Introduction The MMC2107 is the first member of a family of general-purpose microcontrollers (MCU) based on the M•CORE™ M210 central processor unit (CPU low-voltage part, the MMC2107 operates at voltages between 2.7 volts and 3.6 volts particularly suited for use in battery-powered applications. The operating frequency maximum of 33 MHz over a temperature range of – ...

Page 44

... Freescale Semiconductor, Inc. General Description 1.3 Features Features of the MMC2107 include: • • • • • ™OnCE is a trademark of Motorola, Inc. 1. CDR MoneT designates the Motorola one-transistor bitcell. Technical Data 44 M•CORE M210 integer processor: – 32-bit reduced instruction set computer (RISC) architecture – ...

Page 45

... Freescale Semiconductor, Inc. • • • MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Two serial communications interfaces (SCI): – Full-duplex operation – Standard mark/space non-return-to-zero (NRZ) format – 13-bit baud rate selection – Programmable 8-bit or 9-bit data format – ...

Page 46

... Freescale Semiconductor, Inc. General Description • Technical Data 46 – Queue pointers indicate current location for each queue – Automated queue modes initiated by: External edge trigger and gated trigger Periodic/interval timer, within queued analog-to-digital converter (QADC) module {queue1 and queue2} Software command – ...

Page 47

... Freescale Semiconductor, Inc. • • • • • • MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, External interrupts supported: – Rising/falling edge select – Low-level sensitive – Ability for software generation of external interrupt event – General-purpose input/output support Periodic interval timer: – ...

Page 48

... Freescale Semiconductor, Inc. General Description • • • • 1.4 Block Diagram The basic structure of the MMC2107 is shown in Technical Data 48 General-purpose input/output (GPIO): – bits of GPIO – Coherent 32-bit control – Bit manipulation supported via set/clear functions – Unused peripheral pins may be used as extra GPIO. ...

Page 49

... Freescale Semiconductor, Inc. JTAG TAP OnCE M•CORE (M210) INTERRUPT CONTROLLER EDGE INT[7:0] PORT TIM2 TIM1 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, SRAM 8-KBYTE M•CORE BUS IPBUS INTERFACE PROGRAMMABLE INTERVAL TIMER 1 PROGRAMMABLE OSC/PLL INTERVAL TIMER 2 WATCHDOG TIMER IPBUS ...

Page 50

... Freescale Semiconductor, Inc. General Description Technical Data 50 General Description For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 51

... Freescale Semiconductor, Inc. Technical Data — MMC2107 2.1 Contents 2.2 2.3 2.4 2.2 Introduction The address map, shown in • • • • MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 2. System Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Address Map Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ...

Page 52

... Freescale Semiconductor, Inc. System Memory Map 2.3 Address Map Technical Data 52 EXTERNAL MEMORY 0x8000_0000 SEE 2.4 Register Map 0x00c0_0000 0x0080_0000 0 Figure 2-1. Address Map System Memory Map For More Information On This Product, Go to: www.freescale.com REGISTERS INTERNAL SRAM 8 KBYTES INTERNAL FLASH 128 KBYTES MMC2107 – ...

Page 53

... Freescale Semiconductor, Inc. Base Address (Hex) 1. See module sections for details of how much of each block is being decoded. Accesses to addresses outside the module memory maps (and also the reserved area 0x00d1_0000–0x7fff_ffff) will not be responded to and will result in a bus monitor transfer error exception ...

Page 54

... Freescale Semiconductor, Inc. System Memory Map 2.4 Register Map Address Register Name Ports (PORTS) Port A Output Data 0x00c0_0000 Register (PORTA) See page 251. Port B Output Data 0x00c0_0001 Register (PORTB) See page 251. Port C Output Data 0x00c0_0002 Register (PORTC) See page 251. ...

Page 55

... Freescale Semiconductor, Inc. Address Register Name Port H Output Data 0x00c0_0007 Register (PORTH) See page 251. Reset: Port I Output Data 0x00c0_0008 Register (PORTI) See page 251. Reset: 0x00c0_0009 Reserved 0x00c0_000b Port A Data Direction 0x00c0_000c Register (DDRA) See page 252. Reset: Port B Data Direction ...

Page 56

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Port F Data Direction 0x00c0_0011 Register (DDRF) See page 252. Port G Data Direction 0x00c0_0012 Register (DDRG) See page 252. Port H Data Direction 0x00c0_0013 Register (DDRH) See page 252. Port I Data Direction 0x00c0_0014 Register (DDRI) See page 252 ...

Page 57

... Freescale Semiconductor, Inc. Address Register Name Port D Pin Data/Set Data Register 0x00c0_001b (PORTDP/SETD) See page 253. Reset: Port E Pin Data/Set Data Register 0x00c0_001c (PORTEP/SETE) See page 253. Reset: Port F Pin Data/Set Data Register 0x00c0_001d (PORTFP/SETF) See page 253. Reset: Port G Pin Data/Set ...

Page 58

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Port B Clear Output 0x00c0_0025 Data Register (CLRB) See page 254. Port C Clear Output 0x00c0_0026 Data Register (CLRC) See page 254. Port D Clear Output 0x00c0_0027 Data Register (CLRD) See page 254. Port E Clear Output ...

Page 59

... Freescale Semiconductor, Inc. Address Register Name Port I Clear Output 0x00c0_002c Data Register (CLRI) See page 254. Reset: 0x00c0_002d Reserved 0x00c0_002f Port C/D Pin Assignment Register 0x00c0_0030 (PCDPAR) See page 255. Reset: See note Port E Pin Assignment Register 0x00c0_0031 (PEPAR) See page 256. ...

Page 60

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Chip Configuration Module (CCM) 0x00c1_0000 Chip Configuration 0x00c1_0001 Register (CCR) See page 94. 0x00c1_0002 Reserved 0x00c1_0003 Reserved 0x00c1_0004 Reset Configuration 0x00c1_0005 Register (RCON) See page 97 Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 7 of 34) ...

Page 61

... Freescale Semiconductor, Inc. Address Register Name 0x00c1_0006 Chip Identification 0x00c1_0007 Register (CIR) See page 99. Reset: Reset: 0x00c1_0008 Chip Test Register 0x00c1_0009 (CTR) See page 100. Reset: Reset: 0x00c1_000a Reserved 0x00c1_000b 0x00c1_000c Unimplemented 0x00c1_000f 0x00c1_0010 Unimplemented 0x00c1_ffff P = Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 8 of 34) MMC2107 – ...

Page 62

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Chip Selects (CS) 0x00c2_0000 Chip Select Control 0x00c2_0001 Register 0 (CSCR0) See page 525. 0x00c2_0002 Chip Select Control 0x00c2_0003 Register 1 (CSCR1) See page 526. 0x00c2_0004 Chip Select Control 0x00c2_0005 Register 2 (CSCR2) See page 526. ...

Page 63

... Freescale Semiconductor, Inc. Address Register Name 0x00c2_0006 Chip Select Control 0x00c2_0007 Register 3 (CSCR3) See page 527. Reset: Reset: 0x00c2_0008 Unimplemented 0x00c2_ffff Clocks (CLOCK) 0x00c3_0000 Synthesizer Control 0x00c3_0001 Register (SYNCR) See page 227. Reset: Reset: 0x00c3_0002 Synthesizer Status Register (SYNSR) See page 230. ...

Page 64

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c3_0003 Synthesizer Test Register (SYNTR) See page 233. 0x00c3_0004 Synthesizer Test 0x00c3_0005 Register 2 (SYNTR2) 0x00c3_0006 See page 234. 0x00c3_0007 0x00c3_0008 Unimplemented 0x00c3_ffff Reset (RESET) Reset Control Register 0x00c4_0000 (RCR) See page 133. ...

Page 65

... Freescale Semiconductor, Inc. Address Register Name Reset Status Register 0x00c4_0001 (RSR) See page 134. Reset: Reset Test Register 0x00c4_0002 (RTR) See page 135. Reset: 0x00c4_0003 Reserved 0x00c4_0004 Unimplemented 0x00c4_ffff Interrupt Controller (INTC) 0x00c5_0000 Interrupt Control Register 0x00c5_0001 (ICR) See page 157. ...

Page 66

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c5_0004 Interrupt Force Register 0x00c5_0005 High (IFRH) 0x00c5_0006 See page 160. 0x00c5_0007 0x00c5_0008 Interrupt Force Register 0x00c5_0009 Low (IFRL) 0x00c5_000a See page 161. 0x00c5_000b P = Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 13 of 34) ...

Page 67

... Freescale Semiconductor, Inc. Address Register Name 0x00c5_000c Interrupt Pending 0x00c5_000d Register (IPR) 0x00c5_000e See page 162. 0x00c5_000f Reset: Reset: Reset: Reset: 0x00c5_0010 Normal Interrupt Enable 0x00c5_0011 Register (NIER) 0x00c5_0012 See page 163. 0x00c5_0013 Reset: Reset: Reset: Reset Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 14 of 34) MMC2107 – ...

Page 68

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c5_0014 Normal Interrupt Pending 0x00c5_0015 Register (NIPR) 0x00c5_0016 See page 164. 0x00c5_0017 0x00c5_0018 Fast Interrupt Enable 0x00c5_0019 Register (FIER) 0x00c5_001a See page 165. 0x00c5_001b P = Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 15 of 34) ...

Page 69

... Freescale Semiconductor, Inc. Address Register Name 0x00c5_001c Fast Interrupt Pending 0x00c5_001d Register (FIPR) 0x00c5_001e See page 166. 0x00c5_001f Reset: Reset: Reset: Reset: 0x00c5_0040 Priority Level Select through Registers 0x00c5_0067 (PLSR39—PLSR0) See page 167. Reset: 0x00c5_0068 Unimplemented 0x00c5_007f 0x00c5_0080 Unimplemented 0x00c5_ffff ...

Page 70

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Edge Port (EPORT) 0x00c6_0000 EPORT Pin Assignment 0x00c6_0001 Register (EPPAR) See page 264. EPORT Data Direction 0x00c6_0002 Register (EPDDR) See page 266. EPORT Port Interrupt 0x00c6_0003 Enable Register (EPIER) See page 267. ...

Page 71

... Freescale Semiconductor, Inc. Address Register Name 0x00c6_0008 Unimplemented 0x00c6_ffff Watchdog Timer (WDT) 0x00c7_0000 Watchdog Control 0x00c7_0001 Register (WCR) See page 275. Reset: Reset: 0x00c7_0002 Watchdog Modulus 0x00c7_0003 Register (WMR) See page 277. Reset: Reset: 0x00c7_0004 Watchdog Count Register 0x00c7_0005 (WCNTR) See page 278. ...

Page 72

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00c7_0006 Watchdog Service 0x00c7_0007 Register (WSR) See page 279. 0x00c7_0008 Unimplemented 0x00c7_ffff Programmable Interrupt Timer 1 (PIT1) and Programming Interrupt Timer 2 (PIT2) Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####. ...

Page 73

... Freescale Semiconductor, Inc. Address Register Name 0x00c8_0004 PIT Count Register 0x00c8_0005 (PCNTR) 0x00c9_0004 See page 289. 0x00c9_0005 Reset: Reset: 0x00c8_0006 Unimplemented 0x00c8_0007 0x00ca_0008 Unimplemented 0x00ca_ffff Queued Analog-to-Digital Converter (QADC) 0x00ca_0000 QADC Module 0x00ca_0001 Configuration Register (QADCMCR) See page 411. Reset: Reset: ...

Page 74

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ca_0004 Reserved 0x00ca_0005 QADC Port A Data 0x00ca_0006 Register (PORTQA) See page 413. QADC Port B Data 0x00ca_0007 Register (PORTQB) See page 413. 0x00ca_0008 QADC Port A Data 0x00ca_0009 Direction Register (DDRQA) See page 415. ...

Page 75

... Freescale Semiconductor, Inc. Address Register Name 0x00ca_000c QADC Control Register 1 0x00ca_000d (QACR1) See page 419. Reset: Reset: 0x00ca_000e QADC Control Register 2 0x00ca_000f (QACR2) See page 422. Reset: Reset: 0x00ca_0010 QADC Status Register 0 0x00ca_0011 (QASR0) See page 427. Reset: Reset Current pin state U = Unaffected Figure 2-2 ...

Page 76

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ca_0012 QADC Status Register 1 0x00ca_0013 (QASR1) See page 436. 0x00ca_0014 Reserved 0x00ca_01ff 0x00ca_0200 Conversion Command 0x00ca_027e Word Register (CCW) See page 437. 0x00ca_0280 Right-Justified Unsigned 0x00ca_02fe Result Register (RJURR) See page 441. ...

Page 77

... Freescale Semiconductor, Inc. Address Register Name 0x00ca_0300 Left-Justified Signed 0x00ca_037e Result Register (LJSRR) See page 442. Reset: Reset: 0x00ca_0380 Left-Justified Unsigned 0x00ca_03fe Result Register (LJURR) See page 442. Reset: Reset: 0x00ca_0400 Unimplemented 0x00ca_ffff Serial Peripheral Interface (SPI) SPI Control Register 1 0x00cb_0000 (SPICR1) See page 376 ...

Page 78

... Freescale Semiconductor, Inc. System Memory Map Address Register Name SPI Baud Rate Register 0x00cb_0002 (SPIBR) See page 379. SPI Status Register 0x00cb_0003 (SPISR) See page 381. 0x00cb_0004 Reserved SPI Data Register 0x00cb_0005 (SPIDR) See page 382. SPI Pullup and Reduced Drive Register ...

Page 79

... Freescale Semiconductor, Inc. Address Register Name 0x00cb_0010 Unimplemented 0x00cb_ffff Serial Communications Interface 1 (SCI1) and Serial Communications Interface 2 (SCI2) Note: Addresses for SCI1 are at 0x00cc_#### and addresses for SCI2 are at 0x00cd_####. SCI Baud Rate 0x00cc_0000 Register High (SCIBDH) 0x00cd_0000 See page 336. ...

Page 80

... Freescale Semiconductor, Inc. System Memory Map Address Register Name SCI Data Register High 0x00cc_0006 (SCIDRH) 0x00cd_0006 See page 345. SCI Data Register Low 0x00cc_0007 (SCIDRL) 0x00cd_0007 See page 345. SCI Pullup and Reduced 0x00cc_0008 Drive Register 0x00cd_0008 (SCIPURD) See page 346. ...

Page 81

... Freescale Semiconductor, Inc. Address Register Name Timer 1 (TIM1) and Timer 2 (TIM2) Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####. Timer Input Capture/ 0x00ce_0000 Output Compare Select 0x00cf_0000 Register (TIMIOS) See page 300. Reset: Timer Compare Force 0x00ce_0001 ...

Page 82

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00ce_0007 Reserved 0x00cf_0007 Timer Toggle on Overflow 0x00ce_0008 Register (TIMTOV) 0x00cf_0008 See page 306. Timer Control 0x00ce_0009 Register 1 (TIMCTL1) 0x00cf_0009 See page 307. 0x00ce_000a Reserved 0x00cf_000a Timer Control 0x00ce_000b Register 2 (TIMCTL2) 0x00cf_000b See page 308. ...

Page 83

... Freescale Semiconductor, Inc. Address Register Name Timer Flag Register 2 0x00ce_000f (TIMFLG2) 0x00cf_000f See page 313. Reset: Timer Channel 0 Register 0x00ce_0010 High (TIMC0H) 0x00cf_0010 See page 314. Reset: Timer Channel 0 Register 0x00ce_0011 Low (TIMC0L) 0x00cf_0011 See page 314. Reset: Timer Channel 1 Register ...

Page 84

... Freescale Semiconductor, Inc. System Memory Map Address Register Name Timer Channel 3 Register 0x00ce_0017 Low (TIMC3L) 0x00cf_0017 See page 314. Pulse Accumulator 0x00ce_0018 Control Register 0x00cf_0018 (TIMPACTL) See page 315. Pulse Accumulator Flag 0x00ce_0019 Register (TIMPAFLG) 0x00cf_0019 See page 317. Pulse Accumulator ...

Page 85

... Freescale Semiconductor, Inc. Address Register Name Timer Test Register 0x00ce_001f (TIMTST) 0x00cf_001f See page 321. Reset: 0x00ce_0020 0x00ce_ffff Unimplemented 0x00cf_0030 0x00cf_ffff Non-Volatile Memory FLASH (CMFR) 0x00d0_0000 CMFR Module 0x00d0_0001 Configuration Register 0x00d0_0002 (CMFRMCR) 0x00d0_0003 See page 188. Reset: Reset: Reset: Reset: ...

Page 86

... Freescale Semiconductor, Inc. System Memory Map Address Register Name 0x00d0_0004 CMFR Module Test 0x00d0_0005 Register (CMFRMTR) 0x00d0_0006 See page 193. 0x00d0_0007 0x00d0_0008 CMFR High-Voltage 0x00d0_0009 Control Register 0x00d0_000a (CMFRCTL) 0x00d0_000b See page 196 Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 33 of 34) ...

Page 87

... Freescale Semiconductor, Inc. Address Register Name 0x00d0_000c Unimplemented 0x00d0_001c 0x00d0_001d Unimplemented 0x7fff_ffff P = Current pin state U = Unaffected Figure 2-2. Register Summary (Sheet 34 of 34) MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Bit Number Bit Access results in the module generating an access termination transfer error. ...

Page 88

... Freescale Semiconductor, Inc. System Memory Map Technical Data 88 System Memory Map For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 89

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Section 3. Chip Configuration Module (CCM) 3.1 Contents 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.3.1 3.7.3.2 3.7.3.3 3.7.3.4 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.9 3.10 MMC2107 – Rev. 2.0 ...

Page 90

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 3.2 Introduction The chip configuration module (CCM) controls the chip configuration and mode of operation. 3.3 Features The CCM performs these operations. • • • • • • 3.4 Modes of Operation The CCM configures the chip for four modes of operation: • ...

Page 91

... Freescale Semiconductor, Inc. 3.4.1 Master Mode In master mode, the internal central processor unit (CPU) can access external memories and peripherals. Full master mode functionality requires the bonding out of the optional pins. The external bus consists of a 32-bit data bus and 23 address lines. Available bus control signals include R/W, TC[2:0], TSIZ[1:0], TA, TEA, OE, and EB[3:0] ...

Page 92

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 3.5 Block Diagram 3.6 Signal Descriptions Table 3-1 information, refer to Name RCON V DDSYN D[31:16] Technical Data 92 RESET CONFIGURATION CHIP MODE SELECTION BOOT DEVICE SELECTION CHIP CONFIGURATION REGISTER RESET CONFIGURATION REGISTER CHIP IDENTIFICATION REGISTER CHIP TEST REGISTER Figure 3-1 ...

Page 93

... Freescale Semiconductor, Inc. 3.7 Memory Map and Registers This subsection provides a description of the memory map and registers. 3.7.1 Programming Model The CCM programming model consists of these registers: • • • • Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug mode and test operations ...

Page 94

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 3.7.2 Memory Map Table 3-3. Chip Configuration Module Memory Map Address Bits 31–16 0x00c1_0000 Chip configuration register (CCR) 0x00c1_0004 Reset configuration register (RCON) 0x00c1_0008 Chip test register (CTR) 0x00c1_000c CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. Writing to reserved addresses has no effect ...

Page 95

... Freescale Semiconductor, Inc. LOAD — Pad Driver Load Bit The LOAD bit selects full or default drive strength for selected pad output drivers. For maximum capacitive load, set the LOAD bit to select full drive strength. For reduced power consumption, clear the LOAD bit to select default drive strength. ...

Page 96

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) SZEN — TSIZ[1:0] Enable Bits This read/write bit enables the TSIZ[1:0] function of the external pins. PSTEN — PSTAT[3:0] Signal Enable Bits This read/write bit enables the PSTAT[3:0] function of the external pins. SHINT — Show Interrupt Bit The SHINT bit allows visibility to any active interrupt request to the processor ...

Page 97

... Freescale Semiconductor, Inc. BMT[1:0] — Bus Monitor Timing Field The BMT field selects the timeout time for the bus monitor as shown in Table Table 3-2 3.7.3.2 Reset Configuration Register The reset configuration register (RCON read-only register; writing to RCON has no effect. At reset, RCON determines the default operation of certain chip functions ...

Page 98

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) RPLLSEL — PLL Mode Select Bit When the PLL is enabled, the read-only RPLLSEL bit reflects the default PLL mode. The default PLL mode can be overridden during reset configuration. If the default mode is overridden, the PLLSEL bit in the clock module SYNSR reflects the PLL mode. RPLLREF — ...

Page 99

... Freescale Semiconductor, Inc. The default function of the boot select can be overridden during reset configuration. If the default mode is overridden, the CSEN bit in CSCR0 bit reflects the boot device configuration. MODE — Chip Configuration Mode Bit The read-only MODE bit reflects the default chip configuration mode. ...

Page 100

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 3.7.3.4 Chip Test Register The chip test register (CTR) is reserved for factory testing. NOTE: To safeguard against unintentionally activating test logic, write $0000 to the lock-out test features. Setting any bit in CTR may lead to unpredictable results. ...

Page 101

... Freescale Semiconductor, Inc. 3.8.1 Reset Configuration During reset, the pins for the reset override functions are immediately configured to known states, even if the clock source is not present. Table 3-6 D[28, 26, 23:21, 19:16], PA[4, 2], PB[7:5, 3:0] RCON V DDSYN 1. If the external RCON pin is not asserted during reset, pin functions are determined by the default operation mode defined in the RCON register ...

Page 102

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) Table 3-7. Configuration During Reset Default Pin(s) Affected Configuration D[31:0], SHS, TA, TEA CSE[1:0], TC[2:0], OE, RCON0 A[22:0], EB[3:0], CS[3:0] CS[1:0] RCON[3:2] All output pins RCON5 V DDSYN Clock mode RCON[7:6] Internal FLASH configuration 1. Modifying the default configurations is possible only if the external RCON pin is asserted. ...

Page 103

... Freescale Semiconductor, Inc. 3.8.2 Chip Mode Selection The chip mode is selected during reset and reflected in the MODE field of the chip configuration register (CCR). Once reset is exited, the operating mode cannot be changed. selection during reset configuration. Chip Configuration Master mode Single-chip mode ...

Page 104

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) Chip select disabled (32-bit port size) Chip select enabled with 16-bit port size Chip select enabled with 32-bit port size 1. CSCR1 CSEN is initially set only in emulation mode when booting from internal memory and is cleared otherwise. ...

Page 105

... Freescale Semiconductor, Inc. 3.8.4 Output Pad Strength Configuration Output pad strength is determined during reset configuration as shown in Table can be changed by programming the LOAD bit of the chip configuration register. Output pads configured for default strength Output pads configured for full strength 1. Modifying the default configurations is possible only if the external RCON pin is asserted low ...

Page 106

... Freescale Semiconductor, Inc. Chip Configuration Module (CCM) 3.8.6 Internal FLASH Configuration During reset configuration, the D28 pin controls whether or not the internal FLASH is enabled or disabled as shown in Internal FLASH enabled Internal FLASH disabled 1. Modifying the default configurations is possible only if the external RCON pin is asserted low ...

Page 107

... Freescale Semiconductor, Inc. Technical Data — MMC2107 4.1 Contents 4.2 4.3 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.4 4.5.3 4.5.3.1 4.5.3.2 4.5.3.3 4.5.3.4 4.5.3.5 4.5.3.6 4.5.3.7 4.5.3.8 4.5.3.9 4.5.3.10 4.5.3.11 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 4 ...

Page 108

... Freescale Semiconductor, Inc. Signal Description 4.5.4 4.5.4.1 4.5.4.2 4.5.4.3 4.5.5 4.5.5.1 4.5.5.2 4.5.5.3 4.5.5.4 4.5.6 4.5.6.1 4.5.6.2 4.5.7 4.5.8 4.5.8.1 4.5.8.2 4.5.8.3 4.5.8.4 4.5.9 4.5.9.1 4.5.9.2 4.5.9.3 4.5.9.4 4.5.9.5 4.5.9.6 4.5.10 4.5.11 4.5.11.1 4.5.11.2 4.5.11.3 4.5.11.4 4.5.11.5 Technical Data 108 Edge Port Signals 124 External Interrupts (INT[7:6]) ...

Page 109

... Freescale Semiconductor, Inc. 4.2 Introduction The MMC2107 is available in two packages: • • The optional group of pins includes: • • • • • • • • NOTE: The optional pins are either all present or none of them are present. MMC2107 – Rev. 2.0 ...

Page 110

... Freescale Semiconductor, Inc. Signal Description 4.3 Package Pinout Summary Refer to: • • • 144-Pin Package Technical Data 110 Table 4-1 for a summary of the pinouts for both packages Figure 4-1 and Figure 4-2 for a pictorial view of the pinouts Table 4-2 for a brief description of each signal Table 4-1 ...

Page 111

... Freescale Semiconductor, Inc. 144-Pin Package MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Table 4-1. Package Pinouts (Sheet Pin Number 100-Pin Package — — 29 — — 45 — — — 50 — Signal Description Go to: www.freescale.com Signal Description Package Pinout Summary ...

Page 112

... Freescale Semiconductor, Inc. Signal Description 144-Pin Package Technical Data 112 Table 4-1. Package Pinouts (Sheet Pin Number 100-Pin Package — 60 — — — 65 — — — — 81 — — — Signal Description For More Information On This Product, Go to: www.freescale.com Pin Name ...

Page 113

... Freescale Semiconductor, Inc. 144-Pin Package MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Table 4-1. Package Pinouts (Sheet Pin Number 100-Pin Package 86 — — 96 — — 100 — 101 — 102 69 103 70 104 71 105 72 106 73 107 74 108 75 109 76 110 ...

Page 114

... Freescale Semiconductor, Inc. Signal Description 144-Pin Package Technical Data 114 Table 4-1. Package Pinouts (Sheet Pin Number 100-Pin Package 116 — 117 — 118 83 119 — 120 84 121 — 122 — 123 85 124 86 125 87 126 88 127 89 128 90 129 91 130 92 131 — ...

Page 115

... Freescale Semiconductor, Inc. 1 D30 2 D29 3 D28 4 D27 5 D26 6 A11 7 D25 D24 11 A10 12 D23 D22 16 D21 17 D20 D19 21 D18 22 D17 D16 D15 D14 31 D13 D12 35 D11 36 D10 Figure 4-1. 144-Pin LQFP Assignments MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Signal Description Go to: www ...

Page 116

... Freescale Semiconductor, Inc. Signal Description PA6 1 PA5 2 PA4 3 PA3 4 PA2 5 PA1 6 PA0 7 PB7 8 PB6 9 PB5 10 PB4 PB3 14 PB2 15 PB1 16 PB0 17 PC7 18 PC6 19 PC5 PC4 23 PC3 24 PC2 25 Figure 4-2. 100-Pin LQFP Assignments Technical Data 116 Signal Description For More Information On This Product, Go to: www ...

Page 117

... Freescale Semiconductor, Inc. Table 4-2. Signal Descriptions (Sheet (1) Alternate Name RESET — RSTOUT SHOWINT EXTAL — XTAL — CLKOUT — V — DDSYN V — SSSYN PA[7:0], PB[7:0] D[31:0] PC[7:0], PD[7:0] SHS RCON / PE7 TA PE6 TEA PE5 CSE[1:0] PE[4:3] TC[2:0] PE[2:0] R/W PF7 ...

Page 118

... Freescale Semiconductor, Inc. Signal Description Table 4-2. Signal Descriptions (Sheet (1) Alternate Name MOSI GPIO MISO GPIO SCK GPIO SS GPIO Serial Communication Interface (SCI1 and SCI2) TXD1 GPIO RXD1 GPIO TXD2 GPIO RXD2 GPIO ICOC13 PAI / GPIO ICOC1[2: GPIO ICOC23 PAI / GPIO ...

Page 119

... Freescale Semiconductor, Inc. Table 4-2. Signal Descriptions (Sheet (1) Alternate Name TRST — TCLK — TMS — TDI — TDO — DE — TEST — V — — DDF V — SSF V — STBY V — — — — SS Total Total with optional pins 1. Shaded signals are for optional bond-out for 144-pin package. ...

Page 120

... Freescale Semiconductor, Inc. Signal Description 4.4 MMC2107 Specific Implementation Signal Issues Most modules are designed to allow expanded capabilities if all the module signals to the pads are implemented. This subsection discusses how these modules are implemented on the MMC2107. 4.4.1 RSTOUT Signal Functions The RSTOUT signal has these multiple functions: • ...

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... Freescale Semiconductor, Inc. 4.4.2 INT Signal Functions The INT signals have these multiple functions: • • NOTE: If the SZEN or PSTEN bits are set during emulation mode, then the corresponding edge port INT functions are lost and will not be emulated externally. The default reset values for PUPSCI1 and PUPSCI0 will be 0. Thus, the pullup function is disabled by default ...

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... Freescale Semiconductor, Inc. Signal Description 4.5.2 Phase-Lock Loop (PLL) and Clock Signals These signals are used to support the on-chip clock generation circuitry. 4.5.2.1 External Clock In (EXTAL) This input signal is always driven by an external clock input except when used as a connection to the external crystal when the internal oscillator circuit is used ...

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... Freescale Semiconductor, Inc. 4.5.3.2 Show Cycle Strobe (SHS) This output signal is used in emulation mode as a strobe for capturing addresses, controls, and data during show cycles. This signal is also used as RCON. NOTE: This input signal, used only during reset, indicates whether the states on the external signals affect the chip configuration ...

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... Freescale Semiconductor, Inc. Signal Description 4.5.3.8 Address Bus (A[22:0]) These output signals provide the address for the current bus transfer. 4.5.3.9 Enable Byte (EB[3:0]) These output signals indicate which byte of data is valid during external cycles. 4.5.3.10 Chip Select (CS[3:0]) These output signals select external devices for external bus transactions ...

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... Freescale Semiconductor, Inc. 4.5.4.3 External Interrupts (INT[1:0]) These bidirectional signals function as either external interrupt sources or GPIO. 4.5.5 Serial Peripheral Interface Module Signals These signals are used by the SPI module and may also be configured to be discrete I/O signals. 4.5.5.1 Master Out/Slave In (MOSI) This signal is the serial data output from the SPI in master mode and the serial data input in slave mode ...

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... Freescale Semiconductor, Inc. Signal Description 4.5.6.2 Transmit Data (TXD1 and TXD2) These signals are used for the SCI transmitter data output and are also available for GPIO when not configured for transmitter operation. 4.5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) These signals provide the external interface to the timer functions. They may be configured as general-purpose I/O if the timer output function is not needed ...

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... Freescale Semiconductor, Inc. 4.5.9 Debug and Emulation Support Signals These signals are used as the interface to the on-chip JTAG (Joint Test Action Group) controller and also to interface to the OnCE logic. 4.5.9.1 Test Reset (TRST) This active-low input signal is used to initialize the JTAG and OnCE logic asynchronously ...

Page 128

... Freescale Semiconductor, Inc. Signal Description 4.5.10 Test Signal (TEST) This input signal (TEST) is reserved for factory testing only and should be connected to V 4.5.11 Power and Ground Signals These signals provide system power and ground to the chip. Multiple signals are provided for adequate current capability. All power supply signals must have adequate bypass capacitance for high-frequency noise suppression ...

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... Freescale Semiconductor, Inc. Technical Data — MMC2107 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.7 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.7.1.5 5.7.1.6 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.7.3 5.7.3.1 5.7.3.2 5.8 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 5 ...

Page 130

... Freescale Semiconductor, Inc. Reset Controller Module 5.2 Introduction The reset controller is provided to: • • • 5.3 Features Features of the reset controller module include: • • • Technical Data 130 Determine the cause of reset Assert the appropriate reset signals to the system Keep a history of what caused the reset Six sources of reset: – ...

Page 131

... Freescale Semiconductor, Inc. 5.4 Block Diagram Figure 5-1 5.5 Signals See Table 5-1 For additional information, refer to Name RESET pin RSTOUT pin 1. Pullups are disconnected from pins configured as outputs. 2. RESET is always synchronized except when in low-power stop mode. MMC2107 – Rev. 2.0 ...

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... Freescale Semiconductor, Inc. Reset Controller Module 5.6 Memory Map and Registers The reset controller programming model consists of the following registers: • • • 0x000c4_0000 0x000c4_0001 0x000c4_0002 0x000c4_0003 1. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result cycle termination transfer error. ...

Page 133

... Freescale Semiconductor, Inc. 5.6.1 Reset Control Register The reset control register (RCR) allows software control for requesting a reset or for independently asserting the external RSTOUT pin. RCR is read/write always. Address: 0x000c4_0000 Read: SOFTRST Write: Reset: SOFTRST — Software Reset Request Bit The SOFTRST bit allows software to request a reset. Note that the reset caused by setting this bit clears this bit. FRCRSTOUT — ...

Page 134

... Freescale Semiconductor, Inc. Reset Controller Module 5.6.2 Reset Status Register The reset status register (RSR) contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition ...

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... Freescale Semiconductor, Inc. EXT — External Reset Flag EXT indicates that the last reset was caused by an external device asserting the external RESET pin. LOC — Loss of Clock Reset Flag LOC indicates that the last reset state was caused by a loss of clock detected by the loss of clock circuit. LOL — ...

Page 136

... Freescale Semiconductor, Inc. Reset Controller Module 5.7 Functional Description This subsection provides a functional description of the MMC2107 reset controller module. 5.7.1 Reset Sources Table 5-3 controller. Power on External RESET pin (not stop mode) External RESET pin (during stop mode) Watchdog timer Loss of clock ...

Page 137

... Freescale Semiconductor, Inc. 5.7.1.1 Power-On Reset At power-up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until PLL clock mode is selected, until the PLL achieves phase lock. Then after approximately another 512 cycles, RSTOUT is negated and the part begins operation. 5.7.1.2 External Reset Asserting the external RESET pin for at least four rising CLKOUT edges causes the external reset request to be recognized and latched ...

Page 138

... Freescale Semiconductor, Inc. Reset Controller Module 5.7.1.5 Loss of Lock Reset This reset condition occurs in PLL clock mode when the LOLRE bit in SYNCR is set and the PLL loses lock. The reset controller asserts RSTOUT for approximately 512 cycles after the PLL has acquired lock. ...

Page 139

... Freescale Semiconductor, Inc. 1 LOSS OF CLOCK? 2 LOSS OF LOCK? 3 RESET PIN OR WD TIMEOUT OR SW RESET? 12 NEGATE RSTOUT MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product ENABLE BUS MONITOR N 6 BUS CYCLE COMPLETE ASSERT RSTOUT AND LATCH RESET STATUS 8 RESET NEGATED PLL MODE? ...

Page 140

... Freescale Semiconductor, Inc. Reset Controller Module 5.7.2.2 Internal Reset Request If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2), the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (10). Then the reset control logic may latch the configuration according to the RCON pin level (11, 11A) before negating RSTOUT (12) ...

Page 141

... Freescale Semiconductor, Inc. 5.7.3.2 Reset Status Flags For a power-on reset, the POR bit in RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the POR loss of clock or loss of lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the EXT bit along with the LOC and/or LOL bits are set ...

Page 142

... Freescale Semiconductor, Inc. Reset Controller Module Technical Data 142 Reset Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 143

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Section 6. M•CORE M210 Central Processor Unit (CPU) 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.2 Introduction The M•CORE M210 central processor unit (CPU) architecture is one of the most compact, full 32-bit core implementations available. The ...

Page 144

... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) The streamlined execution engine uses many of the same performance enhancements and implementation techniques incorporated in desktop RISC processors. A strictly defined load/store architecture minimizes control complexity. Use of a fixed, 16-bit instruction encoding significantly lowers the memory bandwidth needed to sustain a high rate of instruction execution, and careful selection of the instruction set allows the code density and overall memory efficiency of the M• ...

Page 145

... Freescale Semiconductor, Inc. 6.4 Microarchitecture Summary Figure 6-1 The processor utilizes a 4-stage pipeline for instruction execution. The instruction fetch, instruction decode/register file read, execute, and register file writeback stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. ...

Page 146

... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Arithmetic and logical operations are executed in a single cycle. Multiplication is implemented with a 2-bit per clock, overlapped-scan, modified Booth algorithm with early-out capability, to reduce execution time for operations with small multipliers. Divide is implemented with a 1-bit per clock early-in algorithm ...

Page 147

... Freescale Semiconductor, Inc. 6.5 Programming Model Figure 6-2 defined differently for supervisor and user privilege modes. By convention, in both modes R15 serves as the link register for subroutine calls typically used as stack pointer. USER PROGRAMMER’S The user programming model consists of 16 general-purpose 32-bit registers (R[15:0]), the 32-bit PC, and the C bit ...

Page 148

... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) The supervisor programming model consists of the user model plus 16 additional 32-bit general-purpose registers (R[15:0]’, or the alternate file), the entire PSR, and a set of status/control registers (CR[12:0]). Setting the S bit in the PSR enables supervisor mode operation. ...

Page 149

... Freescale Semiconductor, Inc. 6.6 Data Format Summary The operand data formats supported by the integer unit are standard two’s-complement data formats. The operand size for each instruction is either explicitly encoded in the instruction (load/store instructions) or implicitly defined by the instruction operation (index operations, byte extraction) ...

Page 150

... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) 6.7 Operand Addressing Capabilities M•CORE accesses all memory operands through load and store instructions, transferring data between the general-purpose registers and memory. Register-plus-four-bit scaled displacement addressing mode is used for load and store instructions addressing byte, half-word, and word data ...

Page 151

... Freescale Semiconductor, Inc. Mnemonic BCLRI BF BGENI BGENR BKPT BMASKI BR BREV BSETI BSR BT BTSTI CLRF CLRT CMPHS CMPLT CMPLTI CMPNE CMPNEI DECF DECGT DECLT DECNE DECT DIVS DIVU DOZE FF1 INCF INCT IXH IXW JMP JMPI JSR JSRI LD.[BHW] LDM LDQ LOOPT ...

Page 152

... Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Mnemonic MFCR MOV MOVI MOVF MOVT MTCR MULT MVC MVCV NOT OR ROTLI RSUB RSUBI RTE RFI SEXTB SEXTH ST.[BHW] STM STQ STOP SUBC SUBU SUBI SYNC TRAP TST TSTNBZ WAIT XOR XSR ...

Page 153

... Freescale Semiconductor, Inc. Technical Data — MMC2107 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.7.2.1 7.7.2.2 7.7.2.3 7.7.2.4 7.7.2.5 7.7.2.6 7.7.2.7 7.7.2.8 7.7.2.9 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.4.1 7.8.4.2 7.8.4.3 7.8.5 MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, Section 7 ...

Page 154

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.2 Introduction The interrupt controller collects requests from multiple interrupt sources and provides an interface to the processor core interrupt logic. 7.3 Features Features of the interrupt controller module include: • • • • • • • • ...

Page 155

... Freescale Semiconductor, Inc. 7.5 Block Diagram INTERRUPT SOURCES PRIORITY OR LEVEL 40 SELECT BITS PLSR PLSR PLSR PLSR Figure 7-1. Interrupt Controller Block Diagram 7.6 External Signals No interrupt controller signals connect off-chip. 7.7 Memory Map and Registers This subsection describes the memory map (see registers. MMC2107 – ...

Page 156

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.7.1 Memory Map Table 7-1. Interrupt Controller Module Memory Map Address Bits 31–24 0x00c5_0000 Interrupt control register (ICR) 0x00c5_0004 0x00c5_0008 0x00c5_000c 0x00c5_0010 0x00c5_0014 0x00c5_0018 0x00c5_001c 0x00c5_0020 through 0x00c5_003c 0x00c5_0040 PLSR0 0x00c5_0044 PLSR4 0x00c5_0048 PLSR8 0x00c5_004c ...

Page 157

... Freescale Semiconductor, Inc. 7.7.2 Registers This subsection contains a description of the interrupt controller module registers. 7.7.2.1 Interrupt Control Register The 16-bit interrupt control register (ICR) selects whether interrupt requests are autovectored or vectored, and if vectored, whether fast interrupts generate a different vector number than normal interrupts. ...

Page 158

... Freescale Semiconductor, Inc. Interrupt Controller Module ME — Mask Enable Bit The read/write ME bit enables interrupt masking. Reset clears ME. MFI — Mask Fast Interrupts Bit The read/write MFI bit enables masking of fast interrupt requests. Reset clears MFI. MASK[4:0] — Interrupt Mask Field The read/write MASK[4:0] field determines which interrupt priority levels are masked ...

Page 159

... Freescale Semiconductor, Inc. 7.7.2.2 Interrupt Status Register The 16-bit, read-only interrupt status register (ISR) reflects the state of the interrupt controller outputs to the M•CORE processor. Writes to this register have no effect and are terminated normally. Address: 0x00c5_0002 and 0x00c5_0003 Read: Write: Reset: Read: ...

Page 160

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.7.2.3 Interrupt Force Registers The two 32-bit read/write interrupt force registers (IFRH and IFRL) individually force interrupt source requests. Address: 0x00c5_0004 through 0x00c5_0007 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: ...

Page 161

... Freescale Semiconductor, Inc. Address: 0x00c5_0008 through 0x00c5_000b Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: IF[39:0] — Interrupt Force Field This read/write field forces interrupt requests at the corresponding source numbers. IFRH and IFRL allow software generation of interrupt requests for functional or debug purposes. Writing bit negates the interrupt request. Reset clears the IF[39:0] field. MMC2107 – ...

Page 162

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.7.2.4 Interrupt Pending Register The 32-bit, read-only interrupt pending register (IPR) reflects any currently pending interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_000c through 0x00c5_000f ...

Page 163

... Freescale Semiconductor, Inc. 7.7.2.5 Normal Interrupt Enable Register The read/write, 32-bit normal interrupt enable register (NIER) individually enables any current pending interrupts which are assigned to each priority level as a normal interrupt source. Enabling an interrupt source which has an asserted request causes that request to become pending, and a request to the M• ...

Page 164

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.7.2.6 Normal Interrupt Pending Register The read-only, 32-bit normal interrupt pending register (NIPR) reflects any currently pending normal interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_0014 through 0x00c5_0017 ...

Page 165

... Freescale Semiconductor, Inc. 7.7.2.7 Fast Interrupt Enable Register The read/write, 32-bit fast interrupt enable register (FIER) enables any current pending interrupts which are assigned at each priority level as a fast interrupt source. Enabling an interrupt source which has an asserted request causes that interrupt to become pending, and a request to the M• ...

Page 166

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.7.2.8 Fast Interrupt Pending Register The read-only, 32-bit fast interrupt pending register (FIPR) reflects any currently pending fast interrupts which are assigned to each priority level. Writes to this register have no effect and are terminated normally. Address: 0x00c5_001c through 0x00c5_001f ...

Page 167

... Freescale Semiconductor, Inc. 7.7.2.9 Priority Level Select Registers There are 40 read/write, 8-bit priority level select registers PLSR0–PLSR39, one for every interrupt source. The PLSRx register assigns a priority level to interrupt source x. Address: 0x00c5_0040 through 0x00c5_0067 Read: Write: Reset: Figure 7-11. Priority Level Select Registers (PLSR0–PLSR39) PLS[4:0] — ...

Page 168

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.8.1 Interrupt Sources and Prioritization Each interrupt source in the system sends a unique signal to the interrupt controller interrupt sources are supported. Each interrupt source can be programmed to one of 32 priority levels using PLSR in the interrupt controller. The highest priority level is 31 and lowest priority level is 0 ...

Page 169

... Freescale Semiconductor, Inc interrupt is pending at a given priority level and both the corresponding FIER and NIER bits are set, then both the corresponding FIPR and NIPR bits are set, assuming these bits are not masked. Fast interrupt requests always have priority over normal interrupt requests, even if the normal interrupt request higher priority level than the highest fast interrupt request ...

Page 170

... Freescale Semiconductor, Inc. Interrupt Controller Module If the AE bit is 0, then each interrupt request is presented with a vector number. The low five bits of the vector number (4–0) are determined based on the highest pending priority, with active fast interrupts having priority over active normal interrupts. The remaining two bits (vector bits 5 and 6) are determined based on whether the interrupt request is a fast interrupt and the setting of the FVE bit ...

Page 171

... Freescale Semiconductor, Inc. 7.8.4 Interrupt Configuration After reset, all interrupts are disabled by default. To properly configure the system to handle interrupt requests, configuration must be performed at three levels: • • • Configure the M•CORE first, the interrupt controller second, and the local interrupt sources last. ...

Page 172

... Freescale Semiconductor, Inc. Interrupt Controller Module 7.8.4.3 Interrupt Source Configuration Each module that is capable of generating an interrupt request has an interrupt request enable/disable bit. To allow the interrupt source to be asserted, set the local interrupt enable bit. Once an interrupt request is asserted, the module keeps the source asserted until the interrupt service routine performs a special sequence to clear the interrupt flag ...

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... Freescale Semiconductor, Inc. Table 7-6. Interrupt Source Assignment (Continued) Source Module Flag 16 C0F Timer channel 0 17 C1F Timer channel 1 18 C2F Timer channel 2 19 TIM1 C3F Timer channel 3 20 TOF Timer overflow 21 PAIF Pulse accumulator input 22 PAOVF Pulse accumulator overflow 23 C0F ...

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... Freescale Semiconductor, Inc. Interrupt Controller Module Technical Data 174 Interrupt Controller Module For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 175

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Section 8. Static Random-Access Memory (SRAM) 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.2 Introduction Features of the static random-access memory (SRAM) include: • • • • • • 8.3 Modes of Operation Access to the SRAM is not restricted in any way. The array can be accessed in all supervisor and user modes. MMC2107 – ...

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... Freescale Semiconductor, Inc. Static Random-Access Memory (SRAM) 8.4 Low-Power Modes In wait, doze, and stop modes, clocks to the SRAM are disabled. No recovery time is required when exiting any low-power mode. 8.5 Standby Power Supply Pin (V The standby power supply pin (V RAM array if V 8.6 Standby Operation ...

Page 177

... Freescale Semiconductor, Inc. 8.7 Reset Operation The SRAM contents are undefined immediately following a power-on reset. SRAM contents are unaffected by system reset synchronous reset occurs during a read or write access, then the access completes normally and any pipelined access in progress is stopped without corruption of the SRAM contents. ...

Page 178

... Freescale Semiconductor, Inc. Static Random-Access Memory (SRAM) Technical Data 178 Static Random-Access Memory (SRAM) For More Information On This Product, Go to: www.freescale.com MMC2107 – Rev. 2.0 MOTOROLA ...

Page 179

... Freescale Semiconductor, Inc. Technical Data — MMC2107 Section 9. Non-Volatile Memory FLASH (CMFR) 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.5 9.6 9.7 9.7.1 9.7.1.1 9.7.1.2 9.7.1.3 9.7.2 9.7.2.1 9.7.2.2 9.8 9.8.1 9.8.2 9.8.3 9.8.4 9.8.4.1 9.8.4.2 9.8.4.3 9.8.4.4 9.8.4.5 MMC2107 – Rev. 2.0 ...

Page 180

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) 9.8.5 9.8.5.1 9.8.5.2 9.8.5.3 9.8.6 9.8.7 9.9 9.10 9.2 Introduction This section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external programming voltage supply, V erase operations are enabled through the use of an internal charge pump ...

Page 181

... Freescale Semiconductor, Inc. 9.3 Features Features of the CMFR module include: • • • • • • • MMC2107 – Rev. 2.0 MOTOROLA For More Information On This Product, MoneT FLASH bitcell 128-Kbyte array size using 16-Kbyte blocks Array block restriction control: – Array block erasing – ...

Page 182

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) 9.4 Modes of Operation This subsection describes the two modes of operation: 1. Stop mode 2. Disabled mode 9.4.1 Stop Mode When the FSTOP bit in the CMFR module configuration register (CMFRMCR) register is set, the CMFR enters a low-power operation mode ...

Page 183

... Freescale Semiconductor, Inc. 9.5 Block Diagram The CMFR is divided into array blocks to allow for independent erase, address attributes restriction, and protection from program and erase for each array block. The size of an array block in the CMFR module is fixed at 16 Kbytes. The total CMFR array is distributed into eight blocks. For ...

Page 184

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) To improve system performance, the BIU accesses information in the array at 32 bytes per access. These 32 bytes are copied in a read page buffer aligned to the low-order addresses. A CMFR array contains two non-overlapping read page buffers. The first read page buffer is associated to the lower array blocks ...

Page 185

... Freescale Semiconductor, Inc. 9.6 Glossary of Terms Array block – CMFR array subdivision is a 16-Kbyte contiguous block of information. Each array block can be erased independently. BIU – Bus interface unit that controls access and operation of the CMFR CMFR – CDR MoneT FLASH ARray Erase interlock write – ...

Page 186

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) Program page buffer – 64 bytes of information used to program the CMFR. This information is aligned to a 64-byte boundary within the CMFR. The CMFR module has eight program page buffers, one per array block. Read page buffer – 32-byte block of information that is read from the CMFR array ...

Page 187

... Freescale Semiconductor, Inc. 9.7.1 Control Registers The control registers control CMFR operation. On reset, the registers are loaded with default reset information. Address 0x00d0_0000 0x00d0_0004 0x00d0_0008 0x00d0_000c through 0x00d0_001f The access time of a CMFR register is one system clock for both read and write accesses. Accesses to unimplemented registers cause the BIU to generate a transfer error exception. MMC2107 – ...

Page 188

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) 9.7.1.1 CMFR Module Configuration Register The CMFR module configuration register (CMFRMCR) controls operation of the CMFR array and BIU. Address: 0x00d0_0000 through 0x00d0_0003 Bit 31 Read: FSTOP Write: Reset: 0 Bit 23 Read: SUPV7 Write: Reset: 1 Bit 15 Read: ...

Page 189

... Freescale Semiconductor, Inc. FSTOP — FLASH Stop Enable Bit The read-always FSTOP bit causes the CMFR to enter a low-power stop mode. Writing has no effect if SES = 1. When FSTOP is set, the BIU continues to operate to allow accesses to CMFRMCR. Accesses to other registers are terminated with bus error. Accesses to the array are ignored ...

Page 190

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) The address range of the shadow information is the entire address range of the array, but the high order array addresses, are not used to encode the location. NOTE: When SIE = 1, only the program page buffer associated with the lowest block can be programmed ...

Page 191

... Freescale Semiconductor, Inc. RSVD24 — Reserved Writing to this read/write bit updates the value but has no effect on functionality. SUPV[7:0] — Supervisor Space Field The read-always SUPV[7:0] field controls supervisor/unrestricted address space assignment of array blocks. The field is writable when the LOCKCTL bit is clear. ...

Page 192

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) PROTECT[7:0] — Block Protect Field The read-always PROTECT[7:0] field protects array blocks from program and erase operations. If LOCKCTL = 1 or SES = 1, writing to PROTECT[7:0] has no effect. Array blocks that correspond PROTECT[7:0] are selected for data address space. ...

Page 193

... Freescale Semiconductor, Inc. 9.7.1.2 CMFR Module Test Register The CMFR module test register (CMFRMTR) controls the CMFR array and BIU. Address: 0x00d0_0004 through 0x00d0_0007 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Figure 9-4. CMFR Module Test Register (CMFRMTR) MMC2107 – ...

Page 194

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) NVR — Negative Voltage Range Select Bit The read-always NVR bit modulates the negative pump output to select the negative voltage range in program and erase modes as shown in no effect when the GDB bit is clear. PAWS[2:0] — Pulse Amplitude/Width Select Field The read-always PAWS[2:0] field selects the pulse drain amplitude and width for program or erase operations ...

Page 195

... Freescale Semiconductor, Inc. GDB — Gate or Drain/Source Select Bit The read-always GDB bit selects gate, source, or drain for voltage modulation. GDB is writable when the SES bit is clear. GDB selects the gate, source, or drain. In programming, GDB selects gate (GDB = 1) or drain (GDB = 0) voltage for amplitude modulation. ...

Page 196

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) 9.7.1.3 CMFR High-Voltage Control Register The CMFR high-voltage control register (CMFRCTL) controls the program and erase operations of the CMFR. Address: 0x00d0_0008 through 0x00d0_000b Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Figure 9-5 ...

Page 197

... Freescale Semiconductor, Inc. EHV HVS RECOVERY Recovery = 48 scaled clocks or 128 clocks The recovery time is the time that the CMFR requires to remove the program or erase voltage from the array before switching to another mode of operation. The recovery time is determined by the SCLKR[2:0] field and the ERASE bit. If SCLKR is not 000, the recovery time the scaled clock periods ...

Page 198

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) SCLKR[2:0] 110 and 111 1. The maximum system clock frequency is 33 MHz. The control of the program/erase pulse timing is divided into three functions. The first term of the timing control is the clock scaling, R. The value determined by the system clock range (SCLKR[2:0]). SCLKR[2:0] defines the base clock of the pulse timer ...

Page 199

... Freescale Semiconductor, Inc. CAUTION: Never stop or alter the system clock frequency during a program or erase operation. Changing the clock frequency during program or erase results in inaccurate pulse widths and variations in the charge pump output. The default reset state of SCLKR[2:0] is 000, giving a clock scaling of 1, and the program or erase pulse is not terminated until EHV is cleared by a software write ...

Page 200

... Freescale Semiconductor, Inc. Non-Volatile Memory FLASH (CMFR) CLKPM[6:0] — Clock Period Multiplier Field The third term of the timing control is the linear clock multiplier, M. The clock period multiplier, CLKPM[6:0], defines a linear multiplier for the program or erase pulse defined by: This allows the program/erase pulse to be from 1 to 128 times the pulse set by the system clock period, SCLKR[2:0] and CLKPE[1:0] ...

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