MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 512

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

External Bus Interface Module (EBI)
19.7.1.1 State 1 (X1)
19.7.1.2 Optional Wait States (X2W)
19.7.1.3 State 2 (X2)
Technical Data
512
The EBI drives the address bus. R/W is driven high to indicate a read
cycle. The TSIZ[1:0] pins are driven to indicate the number of bytes in
the transfer. TC[2:0] pins are driven to indicate the type of access. CS
may be asserted to drive a device.
Later in state 1, OE is asserted. If the EB pins are not configured as write
enables for this cycle, one or more EB pins are also asserted, depending
on the size and position of the data to be transferred.
If either the external TA pin or internal chip-select transfer acknowledge
signal is asserted before the end of state 1, the EBI proceeds to state 2.
Wait states are inserted until the slave asserts the TA pin or the internal
chip-select transfer acknowledge signal is asserted. Wait states are
counted in full clocks.
One-half clock later in state 2, the selected device puts its information on
D[31:16] and/or D[15:0]. One or both half-words of the external data bus
are driven to the internal data bus.
The address bus, R/W, CS, OE, EB, TC, and TSIZ pins remain valid
through state 2 to allow for static memory operation and signal skew.
The slave device asserts data until it detects the negation of OE, after
which it and must remove its data within approximately one-half of a
state. Note that the data bus may not become free until state 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA