MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 370

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Serial Communications Interface Modules (SCI1 and SCI2)
16.17.3 Receive Data Register Full
16.17.4 Idle Receiver Input
16.17.5 Overrun
Technical Data
370
Serial Communications Interface Modules (SCI1 and SCI2)
The RDRF flag is set when the data in the receive shift register transfers
to SCIDRH and SCIDRL. It signals that the received data is available to
be read. If the RIE bit is set in SCICR2, RDRF generates an interrupt
request. Clear RDRF by reading SCISR1 and then reading SCIDRL.
The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive
logic 1s appear on the receiver input. This signals an idle condition on
the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an
interrupt request. Once IDLE is cleared, a valid frame must again set the
RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by
reading SCISR1 with IDLE set and then reading SCIDRL.
The OR flag is set if data is not read from SCIDRL before the receive
shift register receives the stop bit of the next frame. This signals a
receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates
an interrupt request. The data in the shift register is lost, but the data
already in SCIDRH and SCIDRL is not affected. Clear OR by reading
SCISR1 and then reading SCIDRL.
Freescale Semiconductor, Inc.
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MMC2107 – Rev. 2.0
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