MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 458

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
Technical Data
458
Q1
Q2
QS
IDLE
0000
IDLE
Situation S5
events are detected while queue 1 is busy, the trigger overrun error bit
is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the
same when the pause feature is in use in either queue.
The remaining situations, S6 through S11, show the impact of a queue 1
trigger event occurring during queue 2 execution. Queue 1 is higher in
priority, the conversion taking place in queue 2 is aborted, so that there
is not a variable latency time in responding to queue 1 trigger events.
Freescale Semiconductor, Inc.
Q1:
Figure 18-27. CCW Priority Situation 5
For More Information On This Product,
Q2:
Queued Analog-to-Digital Converter (QADC)
T1
1000
C1
ACTIVE
T2
TOR1
TRIG
1011
C2
T2
Go to: www.freescale.com
(Figure
PF1
C1
ACTIVE
0110
PAUSE
18-27) shows that when multiple queue 2 trigger
C2
PF2
0101
PAUSE
T1
1001
C3
ACTIVE
ACTIVE
T2
TOR1
1011
TRIG
C4
T2
CF1
C3
ACTIVE
0010
C4
CF2
IDLE
MMC2107 – Rev. 2.0
IDLE
0000
MOTOROLA