MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 217

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
State
S1
S2
Normal operation: Normal array reads and
Erase hardware interlock write: Normal read
register accesses. Block protect information
and pulse-width timing control can be
modified.
operation. CMFR accepts erase hardware
interlock write to any array location. Normal
register access (except CMFRMCR).
CMFRCTL write cannot set EHV. Register
write (except CMFRMCR) is not erase
hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3.
Table 9-10 Erase Interlock State Descriptions
Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
RESET
Figure 9-10. Erase State Diagram
Non-Volatile Memory FLASH (CMFR)
Go to: www.freescale.com
T1
S2
S1
T2
State
Next
S2
S1
S3
T9
T3
T7
T2 Write ERASE = 1 and SES = 1
T1 Write SES = 0 or a master reset
T3
T6
Hardware interlock: Write to any array
location is erase interlock write. Register
write other than CMFRMCR is not erase
hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3; NVM fuses cleared during high-voltage
pulse
T8
S3
S4
S5
Transition Requirement
Non-Volatile Memory FLASH (CMFR)
T4
T5
Functional Description
Technical Data
217