MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 470

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
18.10.6.3 External Gated Single-Scan Mode
18.10.6.4 Interval Timer Single-Scan Mode
Technical Data
470
The QADC provides external gating for queue 1 only. When external
gated single-scan mode is selected, the input level on the associated
external trigger pin enables and disables queue execution. The polarity
of the external gated signal is fixed so only a high level opens the gate
and a low level closes the gate. Once the gate is open, each CCW is
read and the indicated conversions are performed until the gate is
closed. Software must enable the scan to occur by setting the
single-scan enable bit for queue 1. If a pause in a CCW is encountered,
the pause flag does not become set, and execution continues without
pausing.
While the gate is open, queue 1 executes one time. Each CCW is read
and the indicated conversions are performed until an end-of-queue
condition is encountered. When queue 1 completes, the QADC sets the
completion flag (CF1) and clears the single-scan enable bit. Software
may set the single-scan enable bit again to allow another scan of queue
1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW
completes, execution of queue 1 stops, the single-scan enable bit is
cleared, and the PF1 bit is set. Software can read the CWPQ1 to
determine the last valid conversion in the queue. Software must set the
single-scan enable bit again and should clear the PF1 bit before another
scan of queue 1 is initiated during the next open gate. The start of queue
1 is always the first CCW in the CCW table.
Since the condition of the gate is only sampled after each conversion
during queue execution, closing the gate for a period less than a
conversion time interval does not guarantee the closure will be captured.
Both queues can use the periodic/interval timer in a single-scan queue
operating mode. The timer interval can range from 128 to 128 KQCLK
cycles in binary multiples. When the interval timer single-scan mode is
selected and the software sets the single-scan enable bit in QACR1(2),
the timer begins counting. When the time interval elapses, an internal
trigger event is created to start the queue and the QADC begins
execution with the first CCW.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA