MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 232

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Clock Module
Technical Data
232
LOCK — PLL Lock Flag
LOCS — Sticky Loss Of Clock Flag
In stop mode, if the PLL is intentionally disabled, then the LOCKS bit
reflects the value prior to entering stop mode. However, if FWKUP is
set, then LOCKS is cleared until the PLL regains lock. Once lock is
regained, the LOCKS bit reflects the value prior to entering stop
mode. Furthermore, reading the LOCKS bit at the same time that the
PLL loses lock does not return the current loss of lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal
PLL mode and 1:1 PLL mode, LOCKS is set after reset.
The LOCK flag is set when the PLL is locked. PLL lock occurs when
the synthesized frequency is within approximately 0.75 percent of the
programmed frequency. The PLL loses lock when a frequency
deviation of greater than approximately 1.5 percent occurs. Reading
the LOCK flag at the same time that the PLL loses lock or acquires
lock does not return the current condition of the PLL. The power-on
reset circuit uses the LOCK bit as a condition for releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
The LOCS flag is a sticky indication of whether a loss of clock
condition has occurred at any time since exiting reset in normal PLL
and 1:1 PLL modes. LOCS = 0 when the system clocks are operating
normally. LOCS = 1 when system clocks have failed due to a
reference failure or PLL failure.
After entering stop mode with FWKUP set and the PLL and oscillator
intentionally disabled (STPMD[1:0] = 11), the PLL exits stop mode in
SCM while the oscillator starts up. During this time, LOCS is
temporarily set regardless of LOCEN. It is cleared once the oscillator
comes up and the PLL is attempting to lock.
If a read of the LOCS flag and a loss of clock condition occur
simultaneously, the flag does not reflect the current loss of clock
condition.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = PLL locked
0 = PLL not locked
1 = Loss of clock detected since exiting reset or oscillator not yet
0 = Loss of clock not detected since exiting reset
recovered from exit from stop mode with FWKUP = 1
Go to: www.freescale.com
Clock Module
MMC2107 – Rev. 2.0
MOTOROLA