MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 422

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
18.8.5.3 QADC Control Register 2
Technical Data
422
Address: 0x00ca_000e and 0x00ca_000f
Reset:
Reset:
Read:
Read:
Write:
Write:
Control register 2 (QACR2) is the mode control register for the operation
of queue 2. Software specifies the queue operating mode of queue 2
and may enable a completion and/or a pause interrupt. Most of the bits
are typically written once when the software initializes the QADC and not
changed afterward.
Stop mode resets the register ($007f)
Read: Anytime
Write: Anytime except stop mode
CIE2 — Queue 2 Completion Software Interrupt Enable Bit
CIE2 enables an interrupt upon completion of queue 2. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 2.
Freescale Semiconductor, Inc.
RESUME
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable an interrupt after an end-of-conversion for queue 2.
0 = Disable the queue completion interrupt associated with
Bit 15
CIE2
Bit 7
0
0
Figure 18-10. QADC Control Register 2 (QACR2)
queue 2.
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BQ26
PIE2
14
0
6
1
SSE2
BQ25
13
0
0
5
1
MQ212
BQ24
12
0
4
1
MQ211
BQ23
11
0
3
1
MQ210
BQ22
10
0
2
1
MMC2107 – Rev. 2.0
MQ29
BQ21
9
0
1
1
MOTOROLA
MQ28
BQ20
Bit 8
Bit 0
0
1