MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 245

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

10.8.6.1 Phase and Frequency Detector (PFD)
10.8.6.2 Charge Pump/Loop Filter
MMC2107 – Rev. 2.0
MOTOROLA
The PFD is a dual-latch phase-frequency detector. It compares both the
phase and frequency of the reference and feedback clocks. The
reference clock comes from either the crystal oscillator or an external
clock source. The feedback clock comes from:
When the frequency of the feedback clock equals the frequency of the
reference clock, the PLL is frequency-locked. If the falling edge of the
feedback clock lags the falling edge of the reference clock, the PFD
pulses the UP signal. If the falling edge of the feedback clock leads the
falling edge of the reference clock, the PFD pulses the DOWN signal.
The width of these pulses relative to the reference clock depends on how
much the two clocks lead or lag each other. Once phase lock is
achieved, the PFD continues to pulse the UP and DOWN signals for very
short durations during each reference clock cycle. These short pulses
continually update the PLL and prevent the frequency drift phenomenon
known as dead-banding.
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode
the current magnitude of the charge pump varies with the MFD as shown
in
The UP and DOWN signals from the PFD control whether the charge
pump applies or removes charge, respectively, from the loop filter. The
filter is integrated on the chip.
Table
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Freescale Semiconductor, Inc.
For More Information On This Product,
CLKOUT in 1:1 PLL mode, or
VCO output divided by two if CLKOUT is disabled in 1:1 PLL
mode, or
VCO output divided by the MFD in normal PLL mode
10-9.
Charge Pump Current
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Table 10-9. Charge Pump Current and MFD
Clock Module
1X
2X
4X
in Normal Mode Operation
0
2
6
MFD
MFD < 2
MFD < 6
MFD
Functional Description
Technical Data
Clock Module
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