MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 423

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMC2107 – Rev. 2.0
MOTOROLA
PIE2 — Queue 2 Pause Software Interrupt Enable Bit
SSE2 — Queue 2 Single-Scan Enable Bit
MQ2[12:8] — Queue 2 Operating Mode Field
PIE2 enables an interrupt when queue 2 enters the pause state. The
interrupt request is initiated when conversion is complete for a CCW
that has the pause bit set.
SSE2 enables a single-scan of queue 2 to start after a trigger event
occurs. The SSE2 bit may be set to a 1 during the same write cycle
when the MQ2 bits are set for one of the single-scan queue operating
modes. The single-scan enable bit can be written as a 1 or a 0, but is
always read as a 0, unless a test mode is selected. The SSE2 bit
enables a trigger event to initiate queue execution for any single-scan
operation on queue 2. The QADC clears the SSE2 bit when the
single-scan is complete.
The MQ2 field selects the queue operating mode for queue 2.
Table 18-6
queue 2 operating modes.
Freescale Semiconductor, Inc.
MQ2[12:8]
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable an interrupt after an end-of-conversion for queue 2
0 = Disable the pause interrupt associated with queue 2.
1 = Accept a trigger event to start queue 2 in a single-scan mode.
0 = Trigger events are not accepted for single-scan modes.
00000
00001
00010
00011
00100
00101
00110
00111
01000
which has the pause bit set.
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shows the bits in the MQ2 field which enable different
Table 18-6. Queue 2 Operating Modes
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Queued Analog-to-Digital Converter (QADC)
Operating Modes
Register Descriptions
Technical Data
7
8
9
10
11
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