MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 355

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

16.11.3 Break Frames
16.11.4 Idle Frames
MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
Serial Communications Interface Modules (SCI1 and SCI2)
Setting the SBK bit in SCICR2 loads the transmit shift register with a
break frame. A break frame contains all logic 0s and has no start, stop,
or parity bit. Break frame length depends on the M bit in the SCICR1
register. As long as SBK is set, the SCI continuously loads break frames
into the transmit shift register. After SBK is clear, the transmit shift
register finishes transmitting the last break frame and then transmits at
least one logic 1. The automatic logic 1 at the end of a break frame
guarantees the recognition of the next start bit.
The SCI recognizes a break frame when a start bit is followed by eight
or nine 0 data bits and a 0 where the stop bit should be. Receiving a
break frame has these effects on SCI registers:
An idle frame contains all logic 1s and has no start, stop, or parity bit. Idle
frame length depends on the M bit in the SCICR1 register. The preamble
is a synchronizing idle frame that begins the first transmission after
writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle frame to be sent
after the frame currently being transmitted.
When queueing an idle frame, return the TE bit to logic 1 before the stop
bit of the current frame shifts out to the TXD pin. Setting TE after the stop
bit appears on TXD causes data previously written to SCIDRH and
SCIDRL to be lost toggle TE for a queued idle frame while the TDRE flag
is set and immediately before writing new data to SCIDRH and SCIDRL.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Sets the FE flag
Sets the RDRF flag
Clears the SCIDRH and SCIDRL
May set the OR flag, NF flag, PE flag, or the RAF flag
Go to: www.freescale.com
Serial Communications Interface Modules (SCI1 and SCI2)
Technical Data
Transmitter
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