DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet
DF2110BVTE10
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DF2110BVTE10 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2110B Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that ...
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The H8S/2110B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technology original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and ...
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Main Revisions for This Edition Item Page All 1.2 Block Diagram 2 Figure 1.1 Internal Block Diagram of H8S/2110B 1.3.1 Pin 3 Arrangement Figure 1.2 Pin Arrangement of H8S/2110B 2.4.3 Extended 22 Control Register (EXR) 3.2.3 Serial Timer 53 Control ...
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Item Page 5.6.2 Interrupt Control 81 Mode 1 Figure 5.6 Flowchart of Procedure Up to 6.1 Bus Control 89 Register (BCR) 7.1 Overview 91 7.4.4 Pin Functions 100 7.9.3 Pin Functions 116 8.1 Features 131 Figure 8.1 PWM (D/A) Block ...
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Item Page 8.5 Operation 144 Table 8.5 Position of Pulse to Be Added to Basic Pulse with 12-Bit Conversion Accuracy (CFS = 1) Table 8.6 Position of 145 Pulse to Be Added to Basic Pulse with 10-Bit Conversion Accuracy (CFS ...
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Item Page 9.3.6 Timer Interrupt 153 Enable Register (TIER) 9.3.7 Timer 154 Control/Status Register (TCSR) 10.3.5 Timer 188 Control/Status Register (TCSR) 10.3.10 Timer 190 Connection Register S (TCONRS) Table 10.3 Registers 191 Accessible by TMR_X/TMR_Y 10.7.3 Input Capture 199 Operation ...
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Item Page 13.4.4 Master 308 Receive Operation Figure 13.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) 310 13.4.5 Slave Receive 313 Operation 317 13.4.6 Slave Transmit 320 Operation 13.6 Usage Notes 332 ...
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Item Page 14.4.1 Receive 345 Operation Figure 14.3 Sample Receive Processing Flowchart 14.4.2 transmit 347 Operation Figure 14.5 (1) Sample Transmit Processing Flowchart 15.3.1 Host Interface 365 Control Registers 0 and 1 (HICR0, HICR1) 15.3.7 Status 378 Registers 1 to ...
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Item Page 17.8.1 426 Program/Program- Verify Figure 17.9 Program/Program- Verify Flowchart 18.5 Subclock Input 438, 439 Circuit 19.1.1 Standby 443 Control Register (SBYCR) 19.1.1 Standby 443 Control Register (SBYCR) Table 19.1 Operating Frequency and Wait Time 20.1 Register 460 Addresses ...
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Item Page 21.2.3 On-Chip 506 Peripheral Module Timing Figure 21.19 A/D Converter External Trigger Input Timing Appendix C 513 Package Dimensions Figure C.1 Package Dimensions (FP-100B) Figure C.2 514 Package Dimensions (TFP-100B) Rev. 2.00 Mar 21, 2006 page xiv of ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... Section 2 CPU ...................................................................................................................... 13 2.1 Features ............................................................................................................................. ...
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Memory Indirect—@@aa:8 ................................................................................ 41 2.7.9 Effective Address Calculation ............................................................................. 42 2.8 Processing States............................................................................................................... 44 2.9 Usage Notes ...................................................................................................................... 46 2.9.1 Note on TAS Instruction Usage ........................................................................... 46 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 46 2.9.3 Bit Manipulation Instructions ...
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IRQ Enable Register (IER) .................................................................................. 69 5.3.6 IRQ Status Register (ISR).................................................................................... 70 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 70 5.4 Interrupt Sources............................................................................................................... 73 5.4.1 External Interrupts ............................................................................................... 73 5.4.2 ...
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Port 2 Pull-Up MOS Control Register (P2PCR) .................................................. 98 7.3.4 Pin Functions ....................................................................................................... 98 7.3.5 Port 2 Input Pull-Up MOS ................................................................................... 98 7.4 Port 3................................................................................................................................. 99 7.4.1 Port 3 Data Direction Register (P3DDR)............................................................. 99 7.4.2 Port 3 Data Register ...
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Port A Input Data Register (PAPIN).................................................................... 123 7.11.4 Pin Functions ....................................................................................................... 124 7.11.5 Port A Input Pull-Up MOS .................................................................................. 126 7.12 Port B ................................................................................................................................ 127 7.12.1 Port B Data Direction Register (PBDDR)............................................................ 127 7.12.2 Port B Output Data Register ...
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FRC Clear Timing................................................................................................ 161 9.5.4 Input Capture Input Timing ................................................................................. 161 9.5.5 Buffered Input Capture Input Timing .................................................................. 162 9.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 163 9.5.7 Timing of Output Compare Flag (OCF) setting................................................... 164 9.5.8 ...
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TMR_0 and TMR_1 Cascaded Connection ...................................................................... 197 10.6.1 16-Bit Count Mode .............................................................................................. 197 10.6.2 Compare-Match Count Mode .............................................................................. 197 10.7 TMR_Y and TMR_X Cascaded Connection .................................................................... 198 10.7.1 16-Bit Count Mode .............................................................................................. 198 10.7.2 Compare-Match Count Mode .............................................................................. 198 ...
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Register Descriptions ........................................................................................................ 223 12.3.1 Receive Shift Register (RSR) .............................................................................. 223 12.3.2 Receive Data Register (RDR) .............................................................................. 224 12.3.3 Transmit Data Register (TDR)............................................................................. 224 12.3.4 Transmit Shift Register (TSR) ............................................................................. 224 12.3.5 Serial Mode Register (SMR)................................................................................ 225 12.3.6 Serial ...
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Section Bus Interface (IIC) 13.1 Features ............................................................................................................................. 269 13.2 Input/Output Pins .............................................................................................................. 272 13.3 Register Descriptions ........................................................................................................ 273 2 13.3 Bus Data Register (ICDR) ............................................................................. 273 13.3.2 Slave Address Register (SAR) ............................................................................. 274 13.3.3 ...
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KBF Setting Timing and KCLK Control ............................................................. 353 14.4.7 Receive Timing.................................................................................................... 354 14.4.8 KCLK Fall Interrupt Operation............................................................................ 355 14.5 Usage Notes ...................................................................................................................... 356 14.5.1 KBIOE Setting and KCLK Falling Edge Detection............................................. 356 14.5.2 Module Stop Mode Setting .................................................................................. 356 ...
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Input/Output Pins .............................................................................................................. 415 17.5 Register Descriptions ........................................................................................................ 415 17.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 416 17.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 417 17.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 418 17.6 Operating Modes............................................................................................................... 419 ...
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Medium-Speed Mode........................................................................................................ 449 19.4 Sleep Mode ....................................................................................................................... 450 19.5 Software Standby Mode.................................................................................................... 451 19.6 Hardware Standby Mode .................................................................................................. 452 19.7 Watch Mode...................................................................................................................... 453 19.8 Subsleep Mode.................................................................................................................. 454 19.9 Subactive Mode ................................................................................................................ 455 19.10 Module Stop Mode ........................................................................................................... 456 19.11 ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2110B .............................................................. Figure 1.2 Pin Arrangement of H8S/2110B......................................................................... Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ............................................................ 17 Figure 2.2 Stack Structure in Normal Mode ........................................................................ 17 Figure 2.3 ...
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Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1................................................................................................... 81 Figure 5.7 Interrupt Exception Handling ............................................................................. 82 Figure 5.8 Address Break Block Diagram ........................................................................... 84 Figure 5.9 Address Break Timing Example......................................................................... 86 Figure 5.10 Conflict ...
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Section 10 8-Bit Timer (TMR) Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ....................................... 175 Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ..................................... 176 Figure 10.3 Pulse Output Example ........................................................................................ 192 Figure 10.4 Count Timing ...
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Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. 244 Figure 12.9 Sample Serial Reception Flowchart (1) ............................................................... 246 Figure 12.9 Sample Serial Reception Flowchart (2) ............................................................... 247 Figure 12.10 Example ...
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Figure 13.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)................................................... 306 Figure 13.13 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1).............................................................. 307 Figure ...
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Figure 14.5 (2) Sample Transmit Processing Flowchart.............................................................. 348 Figure 14.6 Transmit Timing .................................................................................................. 348 Figure 14.7 (1) Sample Receive Abort Processing Flowchart ..................................................... 349 Figure 14.7 (2) Sample Receive Abort Processing Flowchart ..................................................... 350 Figure 14.8 Receive Abort and Transmit ...
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Figure 18.4 Example of External Clock Input......................................................................... 435 Figure 18.5 External Clock Input Timing ............................................................................... 436 Figure 18.6 Timing of External Clock Output Stabilization Delay Time ............................... 437 Figure 18.7 Subclock Input Timing ........................................................................................ 438 Figure 18.8 Note on Board ...
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Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode.................................................................. Table 1.2 Pin Functions.......................................................................................................... Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 27 Table 2.2 Operation Notation................................................................................................. 28 Table 2.3 Data Transfer Instructions ...................................................................................... 29 Table 2.4 Arithmetic Operations Instructions ...
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Section 7 I/O Ports Table 7.1 Port Functions of H8S/2110B ................................................................................ 92 Table 7.2 Input Pull-Up MOS States (Port 1) ........................................................................ 96 Table 7.3 Input Pull-Up MOS States (Port 2) ........................................................................ 98 Table 7.4 Input Pull-Up MOS States (Port 3) ...
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Section 12 Serial Communication Interface (SCI) Table 12.1 Pin Configuration ................................................................................................... 223 Table 12.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 232 Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 233 Table 12.3 ...
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Section 17 ROM Table 17.1 Differences between Boot Mode and User Program Mode.................................... 411 Table 17.2 Pin Configuration ................................................................................................... 415 Table 17.3 Operating Modes and ROM ................................................................................... 419 Table 17.4 On-Board Programming Mode Settings................................................................. 419 Table 17.5 Boot Mode Operation............................................................................................. ...
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Rev. 2.00 Mar 21, 2006 page xxxviii of xxxviii ...
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Features High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral function 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) ...
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Section 1 Overview 1.2 Block Diagram RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/SDA0 P96/φ/EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2 P67/TMOX/KIN7/IRQ7 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SDA1 P41/TMO0 P40/TMCI0 1 ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement P13 77 P12 78 P11 79 P10 80 PB3/WUE3 81 PB2/WUE2 ...
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Section 1 Overview 1.3.2 Pin Fuctions in Each Operating Mode Table 1.1 Pin Functions in Each Operating Mode Pin No. Single-Chip Modes FP-100B Mode 2, Mode 3 TFP-100B (EXPE = 0) RES 1 2 XTAL 3 EXTAL 4 VCCB 5 ...
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Pin No. Single-Chip Modes FP-100B Mode 2, Mode 3 TFP-100B (EXPE = 0) 22 P93 23 P92/IRQ0 24 P91/IRQ1 25 P90/IRQ2 26 P60/FTCI/KIN0/TMIX 27 P61/FTOA/KIN1 28 P62/FTIA/KIN2/TMIY 29 P63/FTIB/KIN3 30 (B) PA3/KIN11/PS2AD 31 (B) PA2/KIN10/PS2AC 32 P64/FTIC/KIN4 33 P65/FTID/KIN5 34 ...
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Section 1 Overview Pin No. Single-Chip Modes FP-100B Mode 2, Mode 3 TFP-100B (EXPE = P74 P75 P76* /TMOY* P77 * /ExTMOX * VSS 47 (B) PA1/KIN9 48 (B) PA0/KIN8 ...
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Pin No. Single-Chip Modes FP-100B Mode 2, Mode 3 TFP-100B (EXPE = 0) 65 P22 66 P21 67 P20 68 PB5/WUE5 69 PB4/WUE4 70 VSS 71 VSS 72 P17 73 P16 74 P15 75 P14 76 P13 77 P12 78 ...
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Section 1 Overview Pin No. Single-Chip Modes FP-100B Mode 2, Mode 3 TFP-100B (EXPE = 0) 92 VSS 93 P80/PME 94 P81/GA20 95 P82/CLKRUN 96 P83/LPCPD 97 P84/IRQ3/TxD1 98 P85/IRQ4/RxD1 99 (N) P86/IRQ5/SCK1/SCL1 RESO 100 Notes: The (B) in Pin ...
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Pin Functions Table 1.2 Pin Functions Pin No. FP-100B, Type Symbol TFP-100B I/O Power VCC 36, 37, 59 VCL 9 VCCB 4 VSS 15, 46, 70, 71, 92 Clock XTAL 2 EXTAL 3 17 EXCL 17 Operating MD1 5 ...
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Section 1 Overview Pin No. FP-100B, Type Symbol TFP-100B I/O 16-bit FTIB 29 free- FTIC 32 running FTID 33 timer (FRT) 8-bit timer TMO0 50 (TMR_0, TMO1 53 TMR_1, TMOX 35 ExTMOX * 1 TMR_X, 45 TMOY * 1 TMR_Y) ...
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Pin No. FP-100B, Type Symbol TFP-100B I/O Host LAD3 interface LAD0 (LPC) LFRAME 86 LRESET 87 LCLK 88 SERIRQ 89 LSCI, 90, 91, 93 LSMI, PME GA20 94 CLKRUN 95 LPCPD 96 KIN0 to Keyboard 26 ...
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Section 1 Overview Pin No. FP-100B, Type Symbol TFP-100B I/O I/O ports P17 to P10 P27 to P20 P37 to P30 P47 to P40 P52 to P50 12 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 8-bit register-register divide: 12 states (DIVXU.B) 16 16-bit register-register ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's ...
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) (a) Subroutine Branch Note: * Ignored when returning. Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced ...
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Section 2 CPU Instruction set All instructions and addressing modes can be used. Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. ...
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SP Reserved PC (24 bits) (a) Subroutine Branch Figure 2.4 Stack Structure in Advanced Mode 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space ...
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Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control ...
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General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit ...
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Bit Bit Name Initial Value Undefined 5 H Undefined 4 U Undefined 3 N Undefined 2 Z Undefined 1 V Undefined 0 C Undefined R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI ...
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Section 2 CPU 2.4.5 Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn : General register General register General register R RnH : General register RH RnL ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 LDM * 5 , STM * MOVFPE * Arithmetic ADD, SUB, CMP, NEG operations ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, ...
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Section 2 CPU 2.6.1 Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination) * ...
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Table 2.3 Data Transfer Instructions Size * 1 Instruction Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size * Function ADD B/W/L Rd SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Subtraction on immediate ...
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Table 2.4 Arithmetic Operations Instructions (2) Instruction Size * 1 Function DIVXS B/W Rd Performs signed division on data in two general registers: either 16 bits 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on ...
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Table 2.7 Bit Manipulation Instructions (1) Instruction Size * Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function BXOR B C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the memory ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes ...
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Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and E0 ...
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Section 2 CPU For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Effective Address Calculation Operand is immediate data. PC contents Sign extension Memory contents Memory contents Rev. 2.00 Mar 21, 2006 page 43 of 518 Section 2 ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. Reset state In this state the CPU ...
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End of exception handling Exception-handling state RES = high *1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made to the ...
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Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. ...
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Prior to executing BCLR: P47 P46 Input/output Input Input Pin state Low High level level DDR BCLR instruction executed: BCLR #0, @P4DDR After executing BCLR: P47 P46 Input/output Output Output Pin state Low High level ...
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Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6 R4L ...
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Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU ...
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode. Bit Bit Name Initial Value 7 EXPE 0 6 — All — MDS1 — ...
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System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 1 HIE 0 0 RAME 1 Rev. 2.00 Mar 21, 2006 page 52 of 518 REJ09B0299-0200 R/W Description R/W Host Interface Enable Controls CPU access to the keyboard matrix interrupt, ...
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Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Bit Name Initial Value 7 IICS 0 6 IICX1 0 5 ...
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Section 3 MCU Operating Modes Bit Bit Name Initial Value 3 FLSHE 0 2 — ICKS1 0 0 ICKS0 0 3.3 Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in advanced single-chip ...
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Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. Figure 3.1 Address Map for H8S/2110B (1) Section 3 MCU Operating Modes Mode 2 (EXPE = 0) Advanced mode Single-chip mode ...
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Section 3 MCU Operating Modes Figure 3.2 Address Map for H8S/2110B (2) Rev. 2.00 Mar 21, 2006 page 56 of 518 REJ09B0299-0200 Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM H'DFFF H'E080 Reserved area H'E880 On-chip ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved ...
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Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ...
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Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent ...
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The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception ...
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Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack ...
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Section 5 Interrupt Controller 5.1 Features Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). Priorities settable with ICR An interrupt control ...
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Section 5 Interrupt Controller SYSCR NMIEG NMI input IRQ input KIN input WUE input Internal interrupt request WOVI0 to IBFI3 Interrupt controller Legend: : Interrupt control register ICR : IRQ sense control register ISCR IER : IRQ enable register : ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ7 to IRQ0 Input KIN15 to KIN0 Input WUE7 to WUE0 Input 5.3 Register Descriptions The interrupt controller has the ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is ...
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Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set address break is requested. Bit Bit Name Initial Value 7 CMF 0 6 — All 0 ...
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Section 5 Interrupt Controller BARB Bit Bit Name Initial Value 7 A15 All BARC Bit Bit Name Initial Value 7 A7 All — 0 5.3.4 IRQ Sense Control Registers ...
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ISCRL Bit Bit Name Initial Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 5.3.5 IRQ Enable Register (IER) IER controls the enabling and ...
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Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. Bit Bit Name Initial Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 ...
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KMIMR Bit Bit Name Initial Value 7 KMIMR7 1 6 KMIMR6 0 5 KMIMR5 1 4 KMIMR4 1 3 KMIMR3 1 2 KMIMR2 1 1 KMIMR1 1 0 KMIMR0 1 WUEMRB Bit Bit Name Initial Value 7 WUEMR7 1 6 ...
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Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 Figure ...
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Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 ...
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Section 5 Interrupt Controller When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 ...
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An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and UI bits ...
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Section 5 Interrupt Controller Origin of Interrupt Name Source TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use TMR_X, CMIAY (Compare match A) TMR_Y CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture X) ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted ...
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Section 5 Interrupt Controller 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution ...
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Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR ...
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Section 5 Interrupt Controller interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending interrupt request with interrupt control level ...
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An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt ...
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Section 5 Interrupt Controller Figure 5.7 Interrupt Exception Handling Rev. 2.00 Mar 21, 2006 page 82 of 518 REJ09B0299-0200 ...
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Interrupt Response Times Table 5.5 shows interrupt response times and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times No. ...
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Section 5 Interrupt Controller 5.7 Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR address break interrupt is generated, the address ...
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To use the address break function, set each register as follows: 1. Set a break address in the A23 to A1 bits in BAR. 2. Set the BIE bit in ABRKCR enable the address break. When the ...
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Section 5 Interrupt Controller (1) When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction fetch φ H'0310 Address bus execution Break request signal H'0310 NOP H'0312 NOP H'0314 NOP H'0316 ...
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Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...
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Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. ...
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Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to ...
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Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Bit Bit Name Initial Value 7, 6 — All 0 5 ABW 1 4 AST 1 3 WMS1 0 2 WMS0 0 1 WC1 1 0 WC0 1 Rev. ...
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Overview This LSI has eleven I/O ports (ports 1 to 9*, A, and B). Table 7 summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register ...
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Section 7 I/O Ports Table 7.1 Port Functions of H8S/2110B Port Description Port 1 General I/O port Port 2 General I/O port Port 3 General I/O port also functioning as LPC input/output pins Rev. 2.00 Mar 21, 2006 page 92 ...
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Port Description Port 4 General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, and IIC_1 input/output pins Port 5 General I/O port also functioning as SCI_1 extended input/output and IIC_0 input/output pins Port 6 General I/O port ...
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Section 7 I/O Ports Port Description Port 8 General I/O port also functioning as interrupt input, SCI_1 input/output, LPC input/output, and IIC_1 input/output pins Port 9 General I/O port also functioning as IIC_0 input/output, subclock input, output, and interrupt input ...
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Port 1 Port 8-bit I/O port. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. Port 1 data direction register (P1DDR) Port 1 data ...
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Section 7 I/O Ports 7.2.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off status of the port 1 on-chip input pull-up MOSs. Bit Bit Name Initial Value 7 P17PCR 0 6 P16PCR 0 5 P15PCR 0 4 ...
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Port 2 Port 8-bit I/O port. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. Port 2 data direction register (P2DDR) Port 2 data ...
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Section 7 I/O Ports 7.3.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 on-chip input pull-up MOSs. Bit Bit Name Initial Value 7 P27PCR 0 6 P26PCR 0 5 P25PCR 0 4 P24PCR 0 3 P23PCR ...
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Port 3 Port 8-bit I/O port. Port 3 pins also function as LPC input/output pins. Port 3 has the following registers. Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 pull-up MOS ...
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Section 7 I/O Ports 7.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Bit Bit Name Initial Value 7 P37PCR 0 6 P36PCR 0 5 P35PCR 0 4 ...
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Port 3 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified off on a bit-by-bit basis. Table 7.4 summarizes ...
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Section 7 I/O Ports 7.5.2 Port 4 Data Register (P4DR) P4DR stores output data for port 4. Bit Bit Name Initial Value 7 P47DR 0 6 P46DR 0 5 P45DR 0 4 P44DR 0 3 P43DR 0 2 P42DR 0 ...
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P45/TMRI1 The pin function is switched as shown below according to the status of the P45DDR bit. P45DDR Pin Function Note: * When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as ...
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Section 7 I/O Ports P41/TMO0 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_0 and the P41DDR bit. OS3 to OS0 P41DDR Pin Function P40/TMCI0 The pin ...
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Port 5 Data Register (P5DR) P5DR stores output data for port 5 pins. Bit Bit Name Initial Value 7 All P52DR 0 1 P51DR 0 0 P50DR 0 7.6.3 Pin Functions P52/ExSCK1*/SCL0 The pin function ...
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Section 7 I/O Ports P51/ExRxD1* The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1, the SPS1 bit* in SPSR, and the P51DDR bit. SPS1 * RE P51DDR Pin Function ...
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Port 6 Port 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, TMR_X I/O pins, TMR_Y input pin, key-sense interrupt input pins, and interrupt input pins. The port 6 input level can ...
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Section 7 I/O Ports 7.7.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit Bit Name Initial Value 7 P67DR 0 6 P66DR 0 5 P65DR 0 4 P64DR 0 3 P63DR 0 2 P62DR 0 ...
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System Control Register 2 (SYSCR2) SYSCR2 controls the port 6 operations. Bit Bit Name Initial Value 7 KWUL1 0 6 KWUL0 0 5 P6PUE All 0 0 HI12E 0 R/W Description R/W Key ...
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Section 7 I/O Ports 7.7.5 Pin Functions P67/TMOX/KIN7/IRQ7 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X, the OSX bit * OSX * 2 OS3 to OS0 ...
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P64/FTIC/KIN4 The pin function is switched as shown below according to the status of the P64DDR bit. P64DDR Pin Function Note: * This pin can always be used as the FTIC or KIN4 input pin. P63/FTIB/KIN3 P63DDR Pin Function Note: ...
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Section 7 I/O Ports 7.7.6 Port 6 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified off on a bit-by-bit ...
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Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit Bit Name Initial Value Undefined * 7 P77PIN Undefined * 6 P76PIN Undefined * 5 P75PIN Undefined * 4 P74PIN Undefined * 3 P73PIN ...
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Section 7 I/O Ports 7.8.3 Port 7 Output Data Register (P7ODR) P7ODR stores output for the pins of port 7. Bit Bit Name Initial Value 7 P77ODR 0 6 P76ODR 0 5 P75ODR 0 4 P74ODR 0 3 P73ODR 0 ...
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P75 to P70 The pin function is switched as shown below according to the status of P7nDDR*. P7nDDR * Pin Function Note: * The program development tool (emulator) does not support this function 7.9 Port ...
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Section 7 I/O Ports 7.9.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins (P86 to P80). Bit Bit Name Initial Value P86DR 0 5 P85DR 0 4 P84DR 0 3 P83DR ...
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P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1, the SPS1 bit * SPS1 * 2 RE P85DDR Pin Function P85 input Notes: 1. When the IRQ4E bit ...
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Section 7 I/O Ports P82/CLKRUN The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPC3E to LPC1E HI12E P82DDR Pin ...
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Port 9 Port 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin, subclock input pin, and system clock ( ) output pin. P97 is an NMOS push-pull output. SDA0 ...
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Section 7 I/O Ports 7.10.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Bit Name Initial Value 7 P97DR 0 Undefined * 6 P96DR 5 P95DR 0 4 P94DR 0 3 P93DR 0 ...
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P95 The pin function is switched as shown below according to the status of the P95DDR bit. P95DDR Pin Function P94 The pin function is switched as shown below according to the status of the P94DDR bit. P94DDR Pin Function ...
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Section 7 I/O Ports P90/IRQ2 The pin function is switched as shown below according to the status of the P90DDR bit. P90DDR Pin Function Note: * When the IRQ2E bit in IER is set to 1, this pin is used ...
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Port A Output Data Register (PAODR) PAODR stores output data for port A. Bit Bit Name Initial Value 7 PA7ODR 0 6 PA6ODR 0 5 PA5ODR 0 4 PA4ODR 0 3 PA3ODR 0 2 PA2ODR 0 1 PA1ODR 0 ...
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Section 7 I/O Ports 7.11.4 Pin Functions PA7/KIN15/PS2CD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_2 of the keyboard buffer controller, and the PA7DDR bit. KBIOE PA7DDR Pin Function Note: ...
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PA4/KIN12/PS2BC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA4DDR bit. KBIOE PA4DDR Pin Function Note: * When the KBIOE bit is set ...
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Section 7 I/O Ports PA1/KIN9, PA0/KIN8 The pin function is switched as shown below according to the status of the PAnDDR bit. PAnDDR Pin Function Note: * This pin can always be used as the KINm input pin ...
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Port B Port 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event interrupt input pins function. Port B has the following registers. Port B data direction register (PBDDR) Port B output ...
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Section 7 I/O Ports 7.12.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Bit Bit Name Initial Value Undefined * 7 PB7PIN Undefined * 6 PB6PIN Undefined * 5 PB5PIN Undefined * 4 PB4PIN Undefined * ...
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PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LSMIE bits in HICR0 of host interface (LPC), and the PB0DDR bit. LSMIE HI12E PB0DDR Pin Function Notes: 1. When ...
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Section 7 I/O Ports Rev. 2.00 Mar 21, 2006 page 130 of 518 REJ09B0299-0200 ...
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Section 8 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 8.1 Features Division of ...
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Section 8 14-Bit PWM Timer (PWMX) 8.2 Input/Output Pins Table 8.1 lists the PWM (D/A) module input and output pins. Table 8.1 Pin Configuration Name Abbreviation I/O PWM output pin X0 PWX0 PWM output pin X1 PWX1 8.3 Register Descriptions ...
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PWM (D/A) Counters H and L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When ...
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Section 8 14-Bit PWM Timer (PWMX) 8.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since DADR consists of 16-bit data, DADR transfers data to ...
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DADRB Bit Bit Name Initial Value 15 DA13 1 14 DA12 1 13 DA11 1 12 DA10 1 11 DA9 1 10 DA8 1 9 DA7 1 8 DA6 1 7 DA5 1 6 DA4 1 5 DA3 1 4 ...
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Section 8 14-Bit PWM Timer (PWMX) 8.3.3 PWM (D/A) Control Register (DACR) DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed. Bit Initial Bit Name Value R/W 7 TEST 0 R/W 6 PWME ...
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Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an ...
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Section 8 14-Bit PWM Timer (PWMX) 8.5 Operation A PWM waveform like the one shown in figure 8.2 is output from the PWX pin. The value in DADR corresponds to the total width (T (256 pulses when CFS = 0, ...
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Table 8.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Table 8.3 Settings and Operation ...
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Section 8 14-Bit PWM Timer (PWMX ··· ··· CFS = 0 [base cycle ...
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··· ··· ··· = ...
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Section 8 14-Bit PWM Timer (PWMX) Since the value of the following six bits is B'0000 01, the additional pulse is output at the position of basic pulse No shown in table 8.4. Only 1/256 the basic pulse. ...
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Table 8.4 Position of Pulse to Be Added to Basic Pulse with 14-Bit Conversion Accuracy (CFS = 1) Section 8 14-Bit PWM Timer (PWMX) Rev. 2.00 Mar 21, 2006 page 143 of 518 REJ09B0299-0200 ...
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Section 8 14-Bit PWM Timer (PWMX) Table 8.5 Position of Pulse to Be Added to Basic Pulse with 12-Bit Conversion Accuracy (CFS = 1) Rev. 2.00 Mar 21, 2006 page 144 of 518 REJ09B0299-0200 ...
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Table 8.6 Position of Pulse to Be Added to Basic Pulse with 10-Bit Conversion Accuracy (CFS = 1) Section 8 14-Bit PWM Timer (PWMX) Rev. 2.00 Mar 21, 2006 page 145 of 518 REJ09B0299-0200 ...
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Section 8 14-Bit PWM Timer (PWMX) 8.6 Usage Note 8.6.1 Module Stop Mode Setting PWMX operation can be enabled or disabled using the module stop control register. The initial setting is for PWMX operation to be halted. Register access is ...
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Section 9 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16- bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and ...
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Section 9 16-Bit Free-Running Timer (FRT) Figure 9.1 shows a block diagram of the FRT. External clock FTCI Clock selector FTOA FTOB FTIA Control logic FTIB FTIC FTID Legend: OCRA, OCRB : Output compare register A, B (16-bit) OCRAR,OCRAF : ...
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Input/Output Pins Table 9.1 lists the FRT input and output pins. Table 9.1 Pin Configuration Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input ...
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Section 9 16-Bit Free-Running Timer (FRT) 9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF ...
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Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. ...
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Section 9 16-Bit Free-Running Timer (FRT) 9.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Value 7 ICIAE 0 6 ICIBE 0 5 ICICE 0 4 ICIDE 0 3 OCIAE 0 Rev. 2.00 ...
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Bit Bit Name Initial Value 2 OCIBE 0 1 OVIE 0 0 — 1 9.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit Bit Name Initial Value 7 ICFA 0 ...
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Section 9 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value 6 ICFB 0 5 ICFC 0 4 ICFD 0 Rev. 2.00 Mar 21, 2006 page 154 of 518 REJ09B0299-0200 R/W Description R/(W) * Input Capture Flag B This status ...
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Bit Bit Name Initial Value 3 OCFA 0 2 OCFB 0 1 OVF 0 0 CCLRA 0 Note: * Only 0 can be written to clear the flag. Section 9 16-Bit Free-Running Timer (FRT) R/W Description R/(W) * Output Compare ...
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Section 9 16-Bit Free-Running Timer (FRT) 9.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Bit Name Initial Value ...
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Bit Bit Name Initial Value 1 CKS1 0 0 CKS0 0 9.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls ...
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Section 9 16-Bit Free-Running Timer (FRT) Bit Bit Name Initial Value 4 OCRS 0 3 OEA 0 2 OEB 0 1 OLVLA 0 0 OLVLB 0 Rev. 2.00 Mar 21, 2006 page 158 of 518 REJ09B0299-0200 R/W Description R/W Output ...
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Operation 9.4.1 Pulse Output Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are ...
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Section 9 16-Bit Free-Running Timer (FRT) φ External clock input pin FRC input clock FRC Figure 9.4 Increment Timing with External Clock Source 9.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and ...