DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 110

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 5 Interrupt Controller
5.3.6
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Note:
5.3.7
The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs
(KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0).
Rev. 2.00 Mar 21, 2006 page 70 of 518
REJ09B0299-0200
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
KMIMRA
*
Only 0 can be written, for flag clearing.
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Bit Name
KMIMR15
KMIMR14
KMIMR13
KMIMR12
KMIMR11
KMIMR10
KMIMR9
KMIMR8
IRQ Status Register (ISR)
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and
Wake-Up Event Interrupt Mask Register (WUEMRB)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
1
1
1
1
1
1
1
1
R/W
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
[Setting condition]
When the interrupt source selected by the
ISCR registers occurs
[Clearing conditions]
When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
Description
Keyboard Matrix Interrupt Mask 15 to 8
These bits enable or disable a key-sensing
input interrupt request (KIN15 to KIN8).
0: Enables a key-sensing input interrupt
request
1: Disables a key-sensing input interrupt
request
(n = 7 to 0)