DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 481

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

For operating modes after the reset state is cancelled, this LSI has not only the normal program
execution state but also seven power-down modes in which power consumption is significantly
reduced. In addition, there is also module stop mode in which reduced power consumption can be
achieved by individually stopping on-chip peripheral modules.
19.1
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Medium-speed mode
System clock frequency for the CPU operation can be selected as /2, /4, /8, /16, or /32.
Subactive mode
The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0,
TMR_1, WDT_0, and WDT_1 stop operating.
Sleep mode
The CPU stops but on-chip peripheral modules continue operating.
Subsleep mode
The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1
stop operating.
Watch mode
The CPU and on-chip peripheral modules other than WDT_1 stop operating.
Software standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating.
Hardware standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state.
Module stop mode
Independently of above operating modes, on-chip peripheral modules that are not used can be
stopped individually.
Standby control register (SBYCR)
Low power control register (LPWRCR)
Module stop control register H (MSTPCRH)
Module stop control register L (MSTPCRL)
Register Descriptions
Section 19 Power-Down Modes
Rev. 2.00 Mar 21, 2006 page 441 of 518
Section 19 Power-Down Modes
REJ09B0299-0200