DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 34

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Figure 14.5 (2) Sample Transmit Processing Flowchart.............................................................. 348
Figure 14.6
Figure 14.7 (1) Sample Receive Abort Processing Flowchart ..................................................... 349
Figure 14.7 (2) Sample Receive Abort Processing Flowchart ..................................................... 350
Figure 14.8
Figure 14.9
Figure 14.10 KCLKO and KDO Write Timing......................................................................... 352
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing.................... 353
Figure 14.12 Receive Counter and KBBR Data Load Timing.................................................. 354
Figure 14.13 Example of KCLK Input Fall Interrupt Operation............................................... 355
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing................................ 356
Section 15 Host Interface LPC Interface (LPC)
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 15.5
Figure 15.6
Figure 15.7
Figure 15.8
Section 17 ROM
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
Figure 17.9
Figure 17.10 Erase/Erase-Verify Flowchart.............................................................................. 428
Figure 17.11 Memory Map in Programmer Mode .................................................................... 431
Section 18 Clock Pulse Generator
Figure 18.1
Figure 18.2
Figure 18.3
Rev. 2.00 Mar 21, 2006 page xxxii of xxxviii
Transmit Timing .................................................................................................. 348
Receive Abort and Transmit Start (Transmission/Reception Switchover)
Timing.................................................................................................................. 350
KCLKI and KDI Read Timing............................................................................. 351
Block Diagram of LPC ........................................................................................ 358
Typical LFRAME Timing ................................................................................... 392
Abort Mechanism ................................................................................................ 392
GA20 Output........................................................................................................ 394
Power-Down State Termination Timing.............................................................. 399
SERIRQ Timing................................................................................................... 400
Clock Start Request Timing................................................................................. 402
HIRQ Flowchart (Example of Channel 1) ........................................................... 405
Block Diagram of Flash Memory ........................................................................ 410
Flash Memory State Transitions .......................................................................... 411
Boot Mode ........................................................................................................... 412
User Program Mode (Example) ........................................................................... 413
Flash Memory Block Configuration .................................................................... 414
On-Chip RAM Area in Boot Mode...................................................................... 423
ID Code Area ....................................................................................................... 423
Programming/Erasing Flowchart Example in User Program Mode..................... 424
Program/Program-Verify Flowchart .................................................................... 426
Block Diagram of Clock Pulse Generator............................................................ 433
Typical Connection to Crystal Resonator ............................................................ 434
Equivalent Circuit of Crystal Resonator .............................................................. 434