DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 91

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.2.2
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit
7
and
6
5
4
3
2
Bit Name
INTM1
INTM0
XRST
NMIEG
System Control Register (SYSCR)
Initial Value
All 0
0
0
1
0
R/W
R/W
R
R/W
R
R/W
Description
Reserved
The initial value should not be changed.
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog
timer overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 2.00 Mar 21, 2006 page 51 of 518
Section 3 MCU Operating Modes
REJ09B0299-0200

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