DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 370

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Table 13.10 I
Item
t
t
t
t
t
t
t
(master)
t
(slave)
t
Notes: 1. Does not meet the I
Rev. 2.00 Mar 21, 2006 page 330 of 518
REJ09B0299-0200
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDASO
SDAHO
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
3. Calculated using the I
t
0.5 t
0.5 t
0.5 t
(–t
0.5 t
(–t
1 t
0.5 t
(–t
1 t
(–t
1 t
(–t
3 t
cyc
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions.
– 6t
speed mode: 1300 ns min.).
SCLO
SCLLO
SCLL
cyc
Sr
Sf
Sr
Sr
Sr
Indication
)
)
)
)
)
2
SCLO
SCLO
SCLO
SCLO
SCLO
C Bus Interface (IIC)
2
*
C Bus Timing (with Maximum Influence of t
(–t
*
cyc
3
– 12 t
3
– 1 t
– 1 t
+ 2 t
).
(–t
(–t
– 3 t
Sr
)
Sr
Sf
)
)
cyc
cyc
cyc
cyc
cyc
*
2
Standard mode
High-speed mode –300
Standard mode
High-speed mode –250
Standard mode
High-speed mode –300
Standard mode
High-speed mode –250
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode –300
Standard mode
High-speed mode 0
2
C bus interface specification. Remedial action such as the following
2
C bus specification values (standard mode: 4700 ns min.; high-
Time Indication (at Maximum Transfer Rate) [ns]
t
Influence
(Max.)
–1000
–250
–1000
–250
–1000
–1000
–1000
–1000
0
Sr
/t
Sf
I
Specifi-
cation (Min.)
4000
600
4700
1300
4700
1300
4000
600
4700
600
4000
600
250
100
250
100
0
0
2
C Bus
Sr
/t
2
Sf
C bus interface specifications are
)
5 MHz
4000
950
4750
1000 *
3800 *
750 *
4550
800
9000
2200
4400
1350
3100
400
1300
–1400 *
600
600
=
1
1
1
1
8 MHz
4000
950
4750
1000 *
3875 *
825 *
4625
875
9000
2200
4250
1200
3325
625
2200
–500 *
375
375
=
1
1
1
1
10 MHz
4000
950
4750
1000 *
3900 *
850 *
4650
900
9000
2200
4200
1150
3400
700
2500
–200 *
300
300
=
SCLL
1
1
1
1