DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 19

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

5.4
5.5
5.6
5.7
5.8
Section 6 Bus Controller (BSC)
6.1
Section 7 I/O Ports
7.1
7.2
7.3
5.3.5
5.3.6
5.3.7
Interrupt Sources............................................................................................................... 73
5.4.1
5.4.2
Interrupt Exception Handling Vector Table...................................................................... 74
Interrupt Control Modes and Interrupt Operation ............................................................. 77
5.6.1
5.6.2
5.6.3
5.6.4
Address Break ................................................................................................................... 84
5.7.1
5.7.2
5.7.3
5.7.4
Usage Notes ...................................................................................................................... 87
5.8.1
5.8.2
5.8.3
5.8.4
Register Descriptions ........................................................................................................ 89
6.1.1
6.1.2
Overview........................................................................................................................... 91
Port 1................................................................................................................................. 95
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Port 2................................................................................................................................. 97
7.3.1
7.3.2
IRQ Enable Register (IER) .................................................................................. 69
IRQ Status Register (ISR).................................................................................... 70
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and
Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 70
External Interrupts ............................................................................................... 73
Internal Interrupts................................................................................................. 74
Interrupt Control Mode 0 ..................................................................................... 77
Interrupt Control Mode 1 ..................................................................................... 79
Interrupt Exception Handling Sequence .............................................................. 81
Interrupt Response Times .................................................................................... 83
Features................................................................................................................ 84
Block Diagram ..................................................................................................... 84
Operation ............................................................................................................. 84
Usage Notes ......................................................................................................... 85
Conflict between Interrupt Generation and Disabling ......................................... 87
Instructions that Disable Interrupts ...................................................................... 88
Interrupts during Execution of EEPMOV Instruction.......................................... 88
IRQ Status Register (ISR).................................................................................... 88
Bus Control Register (BCR) ................................................................................ 89
Wait State Control Register (WSCR) .................................................................. 90
Port 1 Data Direction Register (P1DDR)............................................................. 95
Port 1 Data Register (P1DR)................................................................................ 95
Port 1 Pull-Up MOS Control Register (P1PCR) .................................................. 96
Pin Functions ....................................................................................................... 96
Port 1 Input Pull-Up MOS ................................................................................... 96
Port 2 Data Direction Register (P2DDR)............................................................. 97
Port 2 Data Register (P2DR)................................................................................ 97
.............................................................................................................. 91
...................................................................................... 89
Rev. 2.00 Mar 21, 2006 page xvii of xxxviii