DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 408

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Host Interface LPC Interface (LPC)
Bit
0
15.3.2
Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave
processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states.
The pin states can be monitored regardless of the host interface operating state or the operating
state of the functions that use pin multiplexing.
Bit
7
6
5
Rev. 2.00 Mar 21, 2006 page 368 of 518
REJ09B0299-0200
HICR2
Bit Name Initial Value Slave Host Description
LSCIB
Bit Name Initial Value Slave Host Description
GA20
LRST
SDWN
Host Interface Control Registers 2 and 3 (HICR2, HICR3)
0
Undefined
0
0
R/W
R
R/(W) * —
R/(W) * —
R/W
R/W
LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit in HICR1. For details, refer to description on the
LSCIE bit.
GA20 Pin Monitor
LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
1: [Setting condition]
LPCPD pin falling edge detection
Writing 0 after reading SDWN = 1
LPC hardware reset and LPC software reset

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