DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 173

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

8.3.1
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit
(CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-
bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of
16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details,
refer to section 8.4, Bus Master Interface.
Bit Bit Name
7
to
0
Bit Bit Name
7
to
2
1
0
Bit (CPU)
Bit (Counter)
DACNTH
DACNTL
UC7
to
UC0
UC8
to
UC13
—
REGS
PWM (D/A) Counters H and L (DACNTH, DACNTL)
:
:
Initial Value
All 0
Initial Value
All 0
1
1
15
7
14
6
13
5
DACNTH
R/W
R/W
R/W
R/W
R
R/W
12
4
11
3
Description
Upper Up-Counter
Description
Lower Up-Counter
Reserved
This bit is always read as 1 and cannot be modified.
Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed
10
2
9
1
8
0
Rev. 2.00 Mar 21, 2006 page 133 of 518
Section 8 14-Bit PWM Timer (PWMX)
7
8
6
9
10
5
DACNTL
11
4
12
3
REJ09B0299-0200
13
2
1
-
-
REGS
0
-